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Message-ID: <7baff2e1-0901-4a3a-b43b-06f2de6cb50b@linux.intel.com>
Date: Mon, 11 Mar 2024 09:25:09 +0800
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Subject: Re: [PATCH 0/2] KVM: x86/pmu: Globally enable GP counters at "RESET"
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To: Sean Christopherson <seanjc@google.com>,
 Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
 Babu Moger <babu.moger@amd.com>, Sandipan Das <sandipan.das@amd.com>,
 Like Xu <like.xu.linux@gmail.com>, Mingwei Zhang <mizhang@google.com>
References: <20240309013641.1413400-1-seanjc@google.com>
From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
In-Reply-To: <20240309013641.1413400-1-seanjc@google.com>
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On 3/9/2024 9:36 AM, Sean Christopherson wrote:
> Globally enable GP counters in PERF_GLOBAL_CTRL when refreshing a vCPU's
> PMU to emulate the architecturally defined post-RESET behavior of the MSR.
>
> Extend pmu_counters_test.c to verify the behavior.
>
> Note, this is slightly different than what I "posted" before: it keeps
> PERF_GLOBAL_CTRL '0' if there are no counters.  That's technically not
> what the SDM dictates, but I went with the common sense route of
> interpreting the SDM to mean "globally enable all GP counters".
>
> I figured it was much more likely that the SDM writers didn't think
> about virtual CPUs that can have a PMU without any GP counters, versus
> Intel really wanting to set _all_ bits in PERF_GLOBAL_CTRL :-)
>
> Sean Christopherson (2):
>    KVM: x86/pmu: Set enable bits for GP counters in PERF_GLOBAL_CTRL at
>      "RESET"
>    KVM: selftests: Verify post-RESET value of PERF_GLOBAL_CTRL in PMCs
>      test
>
>   arch/x86/kvm/pmu.c                            | 16 +++++++++++++--
>   .../selftests/kvm/x86_64/pmu_counters_test.c  | 20 ++++++++++++++++++-
>   2 files changed, 33 insertions(+), 3 deletions(-)
>
>
> base-commit: 964d0c614c7f71917305a5afdca9178fe8231434

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>

Tested-by: Dapeng Mi <dapeng1.mi@linux.intel.com>