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Message-ID: <8c53aff9-eddf-47e3-939f-a1e2abb8d824@tuxon.dev>
Date: Mon, 11 Mar 2024 07:34:22 +0200
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Subject: Re: [PATCH v4 24/39] clk: at91: sam9x7: add support for HW PLL freq
 dividers
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To: Varshini Rajendran <varshini.rajendran@microchip.com>,
 mturquette@baylibre.com, sboyd@kernel.org, nicolas.ferre@microchip.com,
 alexandre.belloni@bootlin.com, mripard@kernel.org,
 linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-kernel@vger.kernel.org
References: <20240223171342.669133-1-varshini.rajendran@microchip.com>
 <20240223172758.672796-1-varshini.rajendran@microchip.com>
From: claudiu beznea <claudiu.beznea@tuxon.dev>
In-Reply-To: <20240223172758.672796-1-varshini.rajendran@microchip.com>
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On 23.02.2024 19:27, Varshini Rajendran wrote:
> Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system
> PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and
> 4 respectively, both have a hardware divider /2. This has to taken into

to be taken

> account in the software to obtain the right frequencies. Support for the
> same is added in the PLL driver.
> 
> fcorepllack -----> HW Div = 2 -+--> fpllack
>                                |
>                                +--> HW Div = 2 ---> fplladiv2ck
> 
> In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz
> after the hardware divider and the plladiv2 freq is 400 MHz after the
> hardware divider (Given that the DIVPMC is 0).

s/Given/given

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
>  drivers/clk/at91/pmc.h             |  1 +
>  2 files changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index b0314dfd7393..1f80759309c0 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
>  {
>  	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
>  	struct sam9x60_frac *frac = to_sam9x60_frac(core);
> +	unsigned long freq;
>  
> -	return parent_rate * (frac->mul + 1) +
> +	freq = parent_rate * (frac->mul + 1) +
>  		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> +
> +	if (core->layout->div2)
> +		freq >>= 1;
> +
> +	return freq;
>  }
>  
>  static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
> @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
>  	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
>  }
>  
> +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
> +						       unsigned long parent_rate)
> +{
> +	return parent_rate >> 1;
> +}
> +
>  static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
>  					unsigned long *parent_rate,
>  					unsigned long rate)
> @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
>  	.restore_context = sam9x60_div_pll_restore_context,
>  };
>  
> +static const struct clk_ops sam9x60_fixed_div_pll_ops = {
> +	.prepare = sam9x60_div_pll_prepare,
> +	.unprepare = sam9x60_div_pll_unprepare,
> +	.is_prepared = sam9x60_div_pll_is_prepared,
> +	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
> +	.round_rate = sam9x60_div_pll_round_rate,
> +	.save_context = sam9x60_div_pll_save_context,
> +	.restore_context = sam9x60_div_pll_restore_context,
> +};
> +
>  struct clk_hw * __init
>  sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>  			      const char *name, const char *parent_name,
> @@ -725,10 +747,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>  	else
>  		init.parent_names = &parent_name;
>  	init.num_parents = 1;
> -	if (flags & CLK_SET_RATE_GATE)
> -		init.ops = &sam9x60_div_pll_ops;
> -	else
> -		init.ops = &sam9x60_div_pll_ops_chg;
> +
> +	if (layout->div2) {
> +		init.ops = &sam9x60_fixed_div_pll_ops;
> +	} else {
> +		if (flags & CLK_SET_RATE_GATE)
> +			init.ops = &sam9x60_div_pll_ops;
> +		else
> +			init.ops = &sam9x60_div_pll_ops_chg;
> +	}
> +

can't it be something like:

	if (layout->div2)
		// ...
	else if (flags & CLK_SET_RATE_GATE)
		// ...
	else
		//

?
>  	init.flags = flags;
>  
>  	div->core.id = id;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index bb9da35198d9..91d1c6305d95 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -64,6 +64,7 @@ struct clk_pll_layout {
>  	u8 frac_shift;
>  	u8 div_shift;
>  	u8 endiv_shift;
> +	u8 div2;
>  };
>  
>  extern const struct clk_pll_layout at91rm9200_pll_layout;