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Mon, 11 Mar 2024 11:35:54 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by anon-ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 11 Mar 2024 11:35:54 +0000 Received: from ediswmail9.ad.cirrus.com (ediswmail9.ad.cirrus.com [198.61.86.93]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTPS id 7AACC820270; Mon, 11 Mar 2024 11:35:54 +0000 (UTC) Date: Mon, 11 Mar 2024 11:35:53 +0000 From: Charles Keepax To: Andrejs Cainikovs CC: , , , Liam Girdwood , "Mark Brown" , Jaroslav Kysela , Takashi Iwai , Andrejs Cainikovs Subject: Re: [RFC PATCH v1] ASoC: wm8904: enable fll with fixed mclk Message-ID: References: <20240308155831.141229-1-andrejs.cainikovs@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240308155831.141229-1-andrejs.cainikovs@gmail.com> X-Proofpoint-GUID: jZaxHSgbLbEIBShIBsJsTeVhjz7k_AtH X-Proofpoint-ORIG-GUID: jZaxHSgbLbEIBShIBsJsTeVhjz7k_AtH X-Proofpoint-Spam-Reason: safe On Fri, Mar 08, 2024 at 04:58:31PM +0100, Andrejs Cainikovs wrote: > From: Andrejs Cainikovs > > Dear all, > > This is an attempt to change wm8904 for a scenario when reference clock > supposed to be fixed to a particular frequency, but is not configured as > a fixed-clock. While this change is working fine, I'm struggling to > finalize it, not being able to find a proper solution of adding a check > whether we want to use fixed MCLK with codec's FLL or not. I could, of > course, introduce a new device tree property, but do not feel this would > be a proper way forward. Hence, I'm sending out this RFC patch to gather > your valuable feedback. > > DUT: Dahlia carrier board with Verdin TI AM62 SOM. > Audio card configuration can be found in ti/k3-am62-verdin-dahlia.dtsi. At some point one really starts to question if this is really a "simple card" any more. > On systems with a fixed reference clock output rate it > is impossible to use this clock for all audio frequencies. > > Following is an example of playing a 44100Hz audio on a system > with a fixed 25MHz reference clock applied to wm8904 codec, > in combination with simple-audio-card without mclk-fs: > > [ 27.013564] wm8904 1-001a: Target BCLK is 1411200Hz > [ 27.013601] wm8904 1-001a: Using 25000000Hz MCLK > [ 27.013611] wm8904 1-001a: CLK_SYS is 12500000Hz > [ 27.013654] wm8904 1-001a: Selected CLK_SYS_RATIO of 256 > [ 27.013663] wm8904 1-001a: Selected SAMPLE_RATE of 44100Hz > [ 27.013671] wm8904 1-001a: Selected BCLK_DIV of 80 for 1562500Hz BCLK > [ 27.013680] wm8904 1-001a: LRCLK_RATE is 35 > > This leads to a distorted sound and this configuration is unusable. > > On the other hand, configuring simple-audio-card with mclk-fs will > force the system to change MCLK frequency, which supposed to be fixed. > > This change forces to use wm8904 FLL while keeping SoC's MCLK > frequency intact: > > [ 234.108149] wm8904 1-001a: Target BCLK is 1411200Hz > [ 234.108304] wm8904 1-001a: Using 0Hz FLL clock > [ 234.108722] wm8904 1-001a: FLL configured for 25000000Hz->1411200Hz > [ 234.108794] wm8904 1-001a: CLK_SYS is 1411200Hz > [ 234.108835] wm8904 1-001a: Selected CLK_SYS_RATIO of 64 > [ 234.108875] wm8904 1-001a: Selected SAMPLE_RATE of 44100Hz > [ 234.108913] wm8904 1-001a: Selected BCLK_DIV of 10 for 1411200Hz BCLK > [ 234.108955] wm8904 1-001a: LRCLK_RATE is 32 > Hmm... the driver already provides an option to automatically configure the clock. Is the issue here that in your fail case the machine driver never calls wm8904_set_sysclk? Or if it does call it, when and what parameters is it passing? Thanks, Charles