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From: Pratyush Yadav <pratyush@kernel.org>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: =?utf-8?Q?Th=C3=A9o?= Lebrun <theo.lebrun@bootlin.com>,  Mark Brown
 <broonie@kernel.org>,
  Rob Herring <robh+dt@kernel.org>,  Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@linaro.org>,  Conor Dooley <conor+dt@kernel.org>,
  Vaishnav Achath <vaishnav.a@ti.com>,  Thomas Bogendoerfer
 <tsbogend@alpha.franken.de>,  "linux-mtd@lists.infradead.org"
 <linux-mtd@lists.infradead.org>,  Pratyush Yadav <pratyush@kernel.org>,
  Michael Walle <mwalle@kernel.org>,  linux-spi@vger.kernel.org,
  devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
  linux-mips@vger.kernel.org,  Vladimir Kondratiev
 <vladimir.kondratiev@mobileye.com>,  Gregory CLEMENT
 <gregory.clement@bootlin.com>,  Thomas Petazzoni
 <thomas.petazzoni@bootlin.com>,  Tawfik Bayouk
 <tawfik.bayouk@mobileye.com>
Subject: Re: [PATCH 11/11] MIPS: mobileye: eyeq5: add octal flash node to
 eval board DTS
In-Reply-To: <f6b8d9bc-d95a-4d85-a2bc-820b1206fcaf@linaro.org> (Tudor
	Ambarus's message of "Mon, 11 Mar 2024 14:06:10 +0000")
References: <20240308-cdns-qspi-mbly-v1-0-a503856dd205@bootlin.com>
	<20240308-cdns-qspi-mbly-v1-11-a503856dd205@bootlin.com>
	<f6b8d9bc-d95a-4d85-a2bc-820b1206fcaf@linaro.org>
Date: Mon, 11 Mar 2024 15:55:23 +0100
Message-ID: <mafs0v85s95t0.fsf@kernel.org>
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On Mon, Mar 11 2024, Tudor Ambarus wrote:

> On 3/8/24 17:18, Th=C3=A9o Lebrun wrote:
>> Add SPI-NOR octal flash node to evaluation board devicetree.
>>=20
>> Signed-off-by: Th=C3=A9o Lebrun <theo.lebrun@bootlin.com>
>> ---
>>  arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>=20
>> diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot=
/dts/mobileye/eyeq5-epm5.dts
>> index 6898b2d8267d..0e5fee7b680c 100644
>> --- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
>> +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
>> @@ -21,3 +21,18 @@ memory@0 {
>>  		      <0x8 0x02000000 0x0 0x7E000000>;
>>  	};
>>  };
>> +
>> +&ospi {
>> +	flash0: flash@0 {
>> +		compatible =3D "jedec,spi-nor";
>> +		reg =3D <0>; /* chip select */
>> +
>> +		spi-max-frequency =3D <40000000>;
>> +		spi-rx-bus-width =3D <8>;
>> +		cdns,read-delay =3D <1>;
>> +		cdns,tshsl-ns =3D <400>;
>> +		cdns,tsd2d-ns =3D <400>;
>> +		cdns,tchsh-ns =3D <125>;
>> +		cdns,tslch-ns =3D <50>;
>
> These cdns properties look bad, they bypass SPI NOR entirely. I'd check
> if these timings can be determined at SFDP parsing time, then I'd pass
> them to the SPI controller.

I agree, but I don't see any table in SFDP that describes these timings.
So I don't think there is a way to discover them.

>
> I see these properties are already accepted in the bindings file for few
> years now. Something to improve later on.

--=20
Regards,
Pratyush Yadav