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Message-ID: <e3a0ecb1-5fb3-4330-8490-2d113a06b85e@sifive.com>
Date: Mon, 11 Mar 2024 23:49:45 -0500
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Subject: Re: [PATCH v6 0/4] riscv/barrier: tidying up barrier-related macro
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To: Eric Chan <ericchancf@google.com>, paul.walmsley@sifive.com,
 palmer@dabbelt.com, aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
 conor.dooley@microchip.com, parri.andrea@gmail.com,
 emil.renner.berthing@canonical.com
References: <20240217131206.3667544-1-ericchancf@google.com>
From: Samuel Holland <samuel.holland@sifive.com>
In-Reply-To: <20240217131206.3667544-1-ericchancf@google.com>
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On 2024-02-17 7:12 AM, Eric Chan wrote:
> This series makes barrier-related macro more neat and clear.
> This is a follow-up to [0-3], change to multiple patches,
> for readability, create new message thread.
> 
> v5 -> v6: [PATCH 1/4] let this change to pass review by checkpatch.pl
> instead of overwriting again in [PATCH 4/4]. for [PATCH 4/4] change
> the error message example in commit message to make it more relevant
> 
> v4 -> v5: [PATCH 3/4] __atomic_acquire_fence and __atomic_release_fence
> omit-the-fence-on-uniprocessor optimization, and fix the typo of
> RISCV_RELEASE_BARRIER when spliting the patch in v3.
> 
> v3 -> v4: fix [PATCH 1/4] commit message weird line breaks and let
> [PATCH 3/4] fix the form that can pass the checking of checkpatch.pl.
> 
> v2 -> v3: split the patch into multiple patches for one problem per patch.
> Also review the changelog to make the description more precise.
> 
> v1 -> v2: makes compilation pass with allyesconfig instead of
> defconfig only, also satisfy scripts/checkpatch.pl.
> - (__asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"))
> + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); })
> 
> [0](v1/v2) https://lore.kernel.org/lkml/20240209125048.4078639-1-ericchancf@google.com/
> [1] (v3) https://lore.kernel.org/lkml/20240213142856.2416073-1-ericchancf@google.com/
> [2] (v4) https://lore.kernel.org/lkml/20240213200923.2547570-1-ericchancf@google.com/
> [4] (v5) https://lore.kernel.org/lkml/20240213223810.2595804-1-ericchancf@google.com/
> 
> Eric Chan (4):
>   riscv/barrier: Define __{mb,rmb,wmb}
>   riscv/barrier: Define RISCV_FULL_BARRIER
>   riscv/barrier: Consolidate fence definitions
>   riscv/barrier: Resolve checkpatch.pl error
> 
>  arch/riscv/include/asm/atomic.h  | 17 ++++++++---------
>  arch/riscv/include/asm/barrier.h | 21 ++++++++++-----------
>  arch/riscv/include/asm/cmpxchg.h |  5 ++---
>  arch/riscv/include/asm/fence.h   | 10 ++++++++--
>  arch/riscv/include/asm/io.h      |  8 ++++----
>  arch/riscv/include/asm/mmio.h    |  5 +++--
>  arch/riscv/include/asm/mmiowb.h  |  2 +-
>  7 files changed, 36 insertions(+), 32 deletions(-)

For the series:

Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>