Received-SPF: pass (google.com: domain of linux-kernel+bounces-100318-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Message-ID: <6df6db7e-7842-4194-b429-ab7443a18ccb@arinc9.com>
Date: Tue, 12 Mar 2024 17:06:24 +0300
Precedence: bulk
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH] net: dsa: mt7530: disable LEDs before reset
Content-Language: en-US
To: Justin Swartz <justin.swartz@risingedge.co.za>
Cc: Daniel Golle <daniel@makrotopia.org>, DENG Qingfang <dqfext@gmail.com>,
 Sean Wang <sean.wang@mediatek.com>, Andrew Lunn <andrew@lunn.ch>,
 Florian Fainelli <f.fainelli@gmail.com>, Vladimir Oltean
 <olteanv@gmail.com>, "David S. Miller" <davem@davemloft.net>,
 Eric Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>,
 Paolo Abeni <pabeni@redhat.com>, Matthias Brugger <matthias.bgg@gmail.com>,
 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
 netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org
References: <20240305043952.21590-1-justin.swartz@risingedge.co.za>
 <6064ba52-2470-4c56-958c-35632187f148@arinc9.com>
 <d45083788db8b0b1ace051adecfe6a3a@risingedge.co.za>
 <1bfd93f1-36d5-436e-818e-2ebdcf475b44@arinc9.com>
 <0439f80319127b6a4a9c19108bcc0065@risingedge.co.za>
From: =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
In-Reply-To: <0439f80319127b6a4a9c19108bcc0065@risingedge.co.za>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 8bit

On 12.03.2024 15:01, Justin Swartz wrote:
> Arınç
> 
> On 2024-03-12 04:41, Arınç ÜNAL wrote:
>> Wouldn't it be a better idea to increase the delay between
>> reset_control_assert() and reset_control_deassert(), and
>> gpiod_set_value_cansleep(priv->reset, 0) and
>> gpiod_set_value_cansleep(priv->reset, 1) instead of disabling the LED
>> controller and delaying before reset?
> 
> I've done some additional tests to see what the difference would be
> between increasing the reset hold period vs. disabling the LEDs then
> sleeping before reset.
> 
> 
> I wanted to know:
> 
> When an active link is present on Port 3 at boot, what are the
> minimum, maximum and average periods between ESW_P3_LED_0
> going low and the signal inversion that seems to co-incide with
> reset_control_deassert() for each approach?
> 
> 
> I created two patches:
> 
> WITH INCREASED RESET DELAY
> 
> As I submitted a patch that added an intended 1000 - 1100 usec delay
> before reset, I thought it would be fair to increase the reset hold
> period by the same value.
> 
> ---%---
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -2243,11 +2243,11 @@ mt7530_setup(struct dsa_switch *ds)
>           */
>          if (priv->mcm) {
>                  reset_control_assert(priv->rstc);
> -               usleep_range(1000, 1100);
> +               usleep_range(2000, 2200);
>                  reset_control_deassert(priv->rstc);
>          } else {
>                  gpiod_set_value_cansleep(priv->reset, 0);
> -               usleep_range(1000, 1100);
> +               usleep_range(2000, 2200);
>                  gpiod_set_value_cansleep(priv->reset, 1);
>          }
> ---%---
> 
> 
> DISABLE LEDS BEFORE RESET
> 
> Reset hold period unchanged from the intended 1000 - 1100 usec.
> 
> ---%---
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -2238,6 +2238,12 @@ mt7530_setup(struct dsa_switch *ds)
>                  }
>          }
> 
> +       /* Disable LEDs before reset to prevent the MT7530 sampling a
> +        * potentially incorrect HT_XTAL_FSEL value.
> +        */
> +       mt7530_write(priv, MT7530_LED_EN, 0);
> +       usleep_range(1000, 1100);
> +
>          /* Reset whole chip through gpio pin or memory-mapped registers for
>           * different type of hardware
>           */
> ---%---
> 
> 
> I ran 20 tests per patch, applied exclusively. 40 tests in total.
> 
>       <-- ESW_P3_LED_0 Low Period before Reset Deassertion -->
> 
>    TEST    WITH INCREASED RESET DELAY    DISABLE LEDS BEFORE RESET
>       #                        (usec)                       (usec)
> -------------------------------------------------------------------
>       1                           182                         4790
>       2                           370                         3470
>       3                           240                         4635
>       4                          1475                         4850
>       5                            70                         4775
>       6                          2730                         4575
>       7                          3180                         4565
>       8                           265                         5650
>       9                           270                         4690
>      10                          1525                         4450
>      11                          3210                         4735
>      12                           120                         4690
>      13                           185                         4625
>      14                           305                         7020
>      15                          2975                         4720
>      16                           245                         4675
>      17                           350                         4740
>      18                            80                        17920
>      19                           150                        17665
>      20                           100                         4620
> 
>     Min                            70                         3470
>     Max                          3210                        17920
> 
>    Mean                           270                         4720
>     Avg                       923.421                     6161.579
> 
> 
> Every test resulted in a 40MHz HT_XTAL_FSEL, but after seeing 70 usec
> and 80 usec periods I wondered how many more tests it may take before
> an 25MHz HT_XTAL_FSEL appears.
> 
> I was also surprised by the 17920 usec and 17665 usec periods listed
> under the DISABLED LEDS BEFORE RESET column. Nothing unusual seemed
> to be happening, at least as far as the kernel message output was
> concerned.
> 
> What do you make of these results?

What I see is setting ESW_P3_LED_0 low via reset assertion is much more
efficient than doing so by setting the LED controller off. So I'd prefer
increasing the delay between assertion and reassertion. For example, the
Realtek DSA subdriver has a much more generous delay. 25ms after reset
assertion [1].

Looking at your results, 2000 - 2200 usec delay still seems too close, so
let's agree on an amount that will ensure that boards in any circumstances
will have these pins back to the bootstrapping configuration before reset
deassertion. What about 5000 - 5100 usec?

[1] https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/tree/drivers/net/dsa/realtek/rtl83xx.c#n205

Arınç