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Date: Tue, 12 Mar 2024 14:07:31 +0000
From: Conor Dooley <conor@kernel.org>
To: Qingfang Deng <dqfext@gmail.com>
Cc: Inochi Amaoto <inochiama@outlook.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908
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On Mon, Mar 11, 2024 at 03:56:29PM +0800, Qingfang Deng wrote:
> Hi Inochi,
>=20
> On Mon, Mar 11, 2024 at 3:13=E2=80=AFPM Inochi Amaoto <inochiama@outlook.=
com> wrote:
> >
> > On Mon, Mar 11, 2024 at 02:30:18PM +0800, Qingfang Deng wrote:
> > > T-Head C908 has the same IRQ num and CSR as previous C9xx cores, but
> > > reports non-zero marchid and mimpid. Remove the ID checks.
> > >
> >
> > Hi, Qingfang,
> >
> > IIRC, the existed C908 SoC (such as K230) have an early version
> > of C908 core. But C908 core itself may support Sscofpmf.
> > So I do not think removing the ID checks is a good idea. Instead,
> > I suggest adding CPUID of your SoC to this check.
>=20
> As of Feb 2024, the latest C908 revision does not support Sscofpmf.
> You may Google "C908R1S0" to see its user manual.
> But I think you're right. Even though C908 does not have Sscofpmf,
> T-Head may release new SoCs which do have Sscofpmf, and the check will
> break. I will submit a new patch with your suggested changes.

If on an SoC where they have updated vector to 1.0 and implemented both
Zicbom and Svpbmt instead of their custom stuff they did not implement
Sscofpmf I think we can expect they won't move away from their custom
implementation soon.
I do agree that we should not remove the ID checks entirely, but I also
do not want to be adding an ID for every SoC that needs this. I think we
should be getting this information from DT going forward.
The DT parsing is done prior to the application of boot time
alternatives, so I think we could apply the "erratum" based on the DT.

I'm also pretty sure that we can also modify the existing code for the
archid =3D=3D impid =3D=3D 0x0 case to set a pseudo isa extension so that t=
he
perf driver could do call riscv_isa_eextension_available() and not worry
about the specfic conditions in which that is true. It'd be something
like this patch:
https://lore.kernel.org/linux-riscv/20240110073917.2398826-8-peterlin@andes=
tech.com/
Just without removing the archid =3D=3D impid =3D=3D 0x0 case from the erra=
ta
code. If you're lost after reading that, I can probably throw together
some untested code for it.

Thanks,
Conor.

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