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AJvYcCVjmEPzCTBfmiZr1QWUB9NsbVMqE6/oC7D93piPUOLD1kTxe+dvpD754dfEUMI8WKHLpCz2MSA/7H254I9Eg2GljcmLlL3DxgBETXTd X-Gm-Message-State: AOJu0YxIEZ3anhBWWqczcrFkJD1CPCeRiNmko8KOfoQOQWQkiZkP6Miv FtaIovL60B+TyKyy7aM/0NBcTSaN9RRD9JwAMaj+X5XHtf8n9hm6ouVtZ4PHAA4= X-Received: by 2002:a17:902:e74a:b0:1dd:a134:5680 with SMTP id p10-20020a170902e74a00b001dda1345680mr6869873plf.69.1710253408730; Tue, 12 Mar 2024 07:23:28 -0700 (PDT) Received: from localhost ([192.184.165.199]) by smtp.gmail.com with ESMTPSA id jy8-20020a17090342c800b001dd5806eff3sm6836433plb.306.2024.03.12.07.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:23:28 -0700 (PDT) Date: Tue, 12 Mar 2024 07:23:28 -0700 (PDT) X-Google-Original-Date: Tue, 12 Mar 2024 07:23:26 PDT (-0700) Subject: Re: [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller In-Reply-To: <871q93eehn.ffs@tglx> CC: peterlin@andestech.com, acme@kernel.org, adrian.hunter@intel.com, ajones@ventanamicro.com, alexander.shishkin@linux.intel.com, andre.przywara@arm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atishp@atishpatra.org, conor+dt@kernel.org, Conor Dooley , Conor Dooley , devicetree@vger.kernel.org, Evan Green , geert+renesas@glider.be, guoren@kernel.org, Heiko Stuebner , irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, locus84@andestech.com, magnus.damm@gmail.com, Mark Rutland , mingo@redhat.com, n.shubin@yadro.com, namhyung@kernel.org, Paul Walmsley , peterlin@andestech.com, peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, Sunil V L , tim609@andestech.com, uwu@icenowy.me, wens@csie.org, Will Deacon , inochiama@outlook.com, unicorn_wang@outlook.com, wefu@redhat.com, randolph@andestech.com From: Palmer Dabbelt To: tglx@linutronix.de Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit On Fri, 23 Feb 2024 01:06:44 PST (-0800), tglx@linutronix.de wrote: > On Fri, Feb 23 2024 at 09:54, Thomas Gleixner wrote: >> On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote: >>> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote: >>>> Palmer, feel free to take this through the riscv tree. I have no other >>>> changes pending against that driver. >>> >>> Aargh. Spoken too early. This conflicts with Anups AIA series. >>> >>> https://lore.kernel.org/all/20240222094006.1030709-1-apatel@ventanamicro.com >>> >>> So I rather take the pile through my tree and deal with the conflicts >>> localy than inflicting it on next. >> >>> Palmer? >> >> Nah. I just apply the two intc patches localy and give you a tag to pull >> from so we carry both the same commits. Then I can deal with the >> conflicts on my side trivially. > > Here you go: > > git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-for-riscv-02-23-24 > > Contains: > > f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller") > 96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number") > > on top of v6.8-rc1 Sorry I missed this. I just merged this into my testing tree, it might take a bit to show up because I've managed to break my VPN so I can't poke the tester box right now... > > Thanks, > > tglx