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Tue, 12 Mar 2024 10:40:10 -0700 (PDT) Message-ID: Date: Tue, 12 Mar 2024 12:40:09 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] clocksource: timer-riscv: Clear timer interrupt on timer initialization Content-Language: en-US To: Ley Foon Tan , Daniel Lezcano , Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: atishp@rivosinc.com, Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ley Foon Tan , stable@vger.kernel.org References: <20240306172330.255844-1-leyfoon.tan@starfivetech.com> From: Samuel Holland In-Reply-To: <20240306172330.255844-1-leyfoon.tan@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2024-03-06 11:23 AM, Ley Foon Tan wrote: > In the RISC-V specification, the stimecmp register doesn't have a default > value. To prevent the timer interrupt from being triggered during timer > initialization, clear the timer interrupt by writing stimecmp with a > maximum value. > > Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") > Cc: > Signed-off-by: Ley Foon Tan > > --- > v3: > Resolved comment from Samuel Holland. > - Function riscv_clock_event_stop() needs to be called before > clockevents_config_and_register(), move riscv_clock_event_stop(). > > v2: > Resolved comments from Anup. > - Moved riscv_clock_event_stop() to riscv_timer_starting_cpu(). > - Added Fixes tag > --- > drivers/clocksource/timer-riscv.c | 3 +++ > 1 file changed, 3 insertions(+) Reviewed-by: Samuel Holland Tested-by: Samuel Holland