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charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAAPr8GUC/23SzU7DMAwH8FeZeqbIdpwm5cR7IA7Nh1kOtFOLK tC0dyedWBuhHGPl909s+doscU5xaV5O12aOa1rSNOYDqqdT48/D+BHbFHKhISCFiKaVOPqYWum lg2AsywBNvnyZo6Tve9Lbez6f0/I1zT/34BW36l8E0SNixRZaFz1YRO8I6XVO67Sk0T/76bPZU lYqpIJdUpbkXUdqcOhQKlIdklDtUm1vGo3akrLRmYrkh2RA2BteOcvAXkhcDzqoitSltLvUWQ4 DRo3BEFHtt10p+112WQIjdtkya1+RppB4zNZkaaxAhxwxOKhIW8pulzZLVgPnqbEAYUX2haRjt v32JubvOok2mJpEKCkfqwDbjEj3BoUVYKhZPCwVreK2RxEVGSEtEWu9Ih1WlXbbJBDFIADs4/9 9uN1uv40iyc4kAwAA To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra , Alexandre Ghiti X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1710287621; l=3918; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=XX2+/VdM5mhKCZhAjluqbyHqY+H52dZCZSEOzxTDQYM=; b=iDe63BieDVlBvDEubOrVk77TNEJxUHkq9FbutFVORS9XaaUJEGTcCrNlCGaHxB4IU2b09a6yq HqFpMP4qtBbA2AOKshD8M+PGTA+ek+P08cDFlAKWtHCiY0Wq6hEEM6k X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Improve the performance of icache flushing by creating a new prctl flag PR_RISCV_SET_ICACHE_FLUSH_CTX. The interface is left generic to allow for future expansions such as with the proposed J extension [1]. Documentation is also provided to explain the use case. Patch sent to add PR_RISCV_SET_ICACHE_FLUSH_CTX to man-pages [2]. [1] https://github.com/riscv/riscv-j-extension [2] https://lore.kernel.org/linux-man/20240124-fencei_prctl-v1-1-0bddafcef331@rivosinc.com Signed-off-by: Charlie Jenkins --- Changes in v13: - Properly unset thread.force_icache_flush (Samuel) - Add ctx value checking when SMP=n (Samuel) - Remove duplicate bit set (Samuel) - Link to v12: https://lore.kernel.org/r/20240312-fencei-v12-0-0f340f004ce7@rivosinc.com Changes in v12: - Use context.icache_stale_mask instead of thread.icache_stale_mask in PR_RISCV_CTX_SW_FENCEI_OFF (Samuel) - Link to v11: https://lore.kernel.org/r/20240212-fencei-v11-0-e1327f25fe10@rivosinc.com Changes in v11: - Add back PR_RISCV_CTX_SW_FENCEI_OFF (Samuel) - Fix under nosmp (Samuel) - Change set_prev_cpu (Samuel) - Fixup example testcase in docs - Change wording of documentation slightly (Alejandor Colomar) - Link to v10: https://lore.kernel.org/r/20240124-fencei-v10-0-a25971f4301d@rivosinc.com Changes in v10: - Fix fence.i condition to properly only flush on migration (Alex) - Fix documentation wording (Alex) - Link to v9: https://lore.kernel.org/r/20240123-fencei-v9-0-71411bfe8d71@rivosinc.com Changes in v9: - Remove prev_cpu from mm (Alex) - Link to v8: https://lore.kernel.org/r/20240116-fencei-v8-0-43a42134f021@rivosinc.com Changes in v8: - Only flush icache if migrated to different cpu (Alex) - Move flushing to switch_to to catch per-thread flushing properly - Link to v7: https://lore.kernel.org/r/20240112-fencei-v7-0-78f0614e1db0@rivosinc.com Changes in v7: - Change "per_thread" parameter to "scope" and provide constants for the parameter. - Link to v6: https://lore.kernel.org/r/20240109-fencei-v6-0-04116e51445c@rivosinc.com Changes in v6: - Fixup documentation formatting - Link to v5: https://lore.kernel.org/r/20240108-fencei-v5-0-aa1e51d7222f@rivosinc.com Changes in v5: - Minor documentation changes (Randy) - Link to v4: https://lore.kernel.org/r/20240107-fencei-v4-0-d4cf2fb905d3@rivosinc.com Changes in v4: - Add OFF flag to disallow fence.i in userspace (Atish) - Fix documentation issues (Atish) - Link to v3: https://lore.kernel.org/r/20231213-fencei-v3-0-b75158238eb7@rivosinc.com Changes in v3: - Check if value force_icache_flush set on thread, rather than in mm twice (Clément) - Link to v2: https://lore.kernel.org/r/20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com Changes in v2: - Fix kernel-doc comment (Conor) - Link to v1: https://lore.kernel.org/r/20231122-fencei-v1-0-bec0811cb212@rivosinc.com --- Charlie Jenkins (4): riscv: Remove unnecessary irqflags processor.h include riscv: Include riscv_set_icache_flush_ctx prctl documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl cpumask: Add assign cpu Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + arch/riscv/include/asm/irqflags.h | 1 - arch/riscv/include/asm/mmu.h | 2 + arch/riscv/include/asm/processor.h | 10 ++++ arch/riscv/include/asm/switch_to.h | 23 ++++++++ arch/riscv/mm/cacheflush.c | 111 +++++++++++++++++++++++++++++++++++++ arch/riscv/mm/context.c | 19 ++++--- include/linux/cpumask.h | 16 ++++++ include/uapi/linux/prctl.h | 6 ++ kernel/sys.c | 6 ++ 11 files changed, 284 insertions(+), 9 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20231117-fencei-f9f60d784fa0 -- - Charlie