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From: Li Ming <ming4.li@intel.com>
To: dan.j.williams@intel.com,
	rrichter@amd.com,
	terry.bowman@amd.com
Cc: linux-cxl@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Li Ming <ming4.li@intel.com>
Subject: [RFC PATCH 0/6] Add support for root port RAS error handling
Date: Wed, 13 Mar 2024 08:35:56 +0000
Message-Id: <20240313083602.239201-1-ming4.li@intel.com>
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Protocol errors signaled to a CXL root port may be captured by a Root
Complex Event Collector(RCEC). If those errors are not cleared and
reported the system owner loses forensic information for system failure
analysis.

Per CXL r3.1 section 9.18.1.5, the recommendation for this case from CXL
specification is the 'Else' statement in 'IMPLEMENTATION NODE' under
'Table 9-24 RDPAS Structure':

	"Probe all CXL Downstream Ports and determine whether they have logged an
	error in the CXL.io or CXL.cachemem status registers."

The CXL subsystem already supports RCH RAS Error handling that has a
dependency on the RCEC. Reuse and extend that RCH topoogy support to
handle reported errors in the VH topology case. The implementation is
composed of:
* Provide a new interface from RCEC side to support walk all devices
  under RCEC and RCEC associated bus range. PCIe AER core uses this
  interface to walk all CXL endpoints and all CXL root ports under the
  bus ranges.

* Update the PCIe AER core to enable Uncorrectable Internal Errors and
  Correctable Internal Errors report for root ports.

* Invoke the cxl_pci error handler for RCEC reported errors.

* Handle root-port errors in the cxl_pci handler when the device is
  direct attached.

The implementation is only for above case without CXL switch, still
remain two opens to be discussed.
1. Is it compatible for CXL switch port error handling?
CXL switch port error handling proposal has not yet been finalized.
Should confirm that this implementation will be compatible with that.

2. How to handle the case which CXL root port reported CXL.CM protocol
erros by itself?
Not support for this case in the patchset at present, my opinion is that
invoking the cxl_pci handle to deal with such case as well.

base-commit: 73bf93edeeea866b0b6efbc8d2595bdaaba7f1a5 branch: next

Li Ming (6):
  PCI/RCEC: Introduce pcie_walk_rcec_all()
  PCI/CXL: A new attribute to indicate if a host bridge is CXL capable
  PCI/AER: Enable RCEC to report internal error for CXL root port
  PCI/AER: Support to handle errors detected by CXL root port
  cxl: Use __free() for cxl_pci/mem_find_port() to drop put_device()
  cxl/pci: Add support for the RAS handling of RCEC captured errors on
    RP

 drivers/acpi/pci_root.c |  1 +
 drivers/cxl/core/pci.c  | 89 +++++++++++++++++++++++++++--------------
 drivers/cxl/core/port.c |  9 +++++
 drivers/cxl/cxl.h       |  2 +
 drivers/cxl/mem.c       |  5 +--
 drivers/cxl/pci.c       | 12 +++---
 drivers/pci/pci.h       |  6 +++
 drivers/pci/pcie/aer.c  | 44 +++++++++++++-------
 drivers/pci/pcie/rcec.c | 44 +++++++++++++++++++-
 include/linux/pci.h     |  1 +
 10 files changed, 155 insertions(+), 58 deletions(-)

-- 
2.40.1