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Thu, 14 Mar 2024 09:13:50 GMT Received: from [10.218.19.46] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Mar 2024 02:13:45 -0700 Message-ID: <1a2a7d7d-ed67-1c90-d3d1-4529dc07effa@quicinc.com> Date: Thu, 14 Mar 2024 14:43:41 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm8150: Add video clock controller node Content-Language: en-US To: Dmitry Baryshkov CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Ajit Pandey , Imran Shaik , Taniya Das , "Jagadeesh Kona" , , , , References: <20240313-videocc-sm8150-dt-node-v1-0-ae8ec3c822c2@quicinc.com> <20240313-videocc-sm8150-dt-node-v1-3-ae8ec3c822c2@quicinc.com> From: "Satya Priya Kakitapalli (Temp)" In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: auCfX0or9HvqZfpgmMkcyFgxbKdz9EES X-Proofpoint-ORIG-GUID: auCfX0or9HvqZfpgmMkcyFgxbKdz9EES X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-14_07,2024-03-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1011 suspectscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403140064 On 3/14/2024 12:46 AM, Dmitry Baryshkov wrote: > On Wed, 13 Mar 2024 at 13:11, Satya Priya Kakitapalli > wrote: >> Add device node for video clock controller on Qualcomm >> SM8150 platform. >> >> Signed-off-by: Satya Priya Kakitapalli >> --- >> arch/arm64/boot/dts/qcom/sa8155p.dtsi | 4 ++++ >> arch/arm64/boot/dts/qcom/sm8150.dtsi | 13 +++++++++++++ >> 2 files changed, 17 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8155p.dtsi b/arch/arm64/boot/dts/qcom/sa8155p.dtsi >> index ffb7ab695213..9e70effc72e1 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8155p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8155p.dtsi >> @@ -38,3 +38,7 @@ &rpmhpd { >> */ >> compatible = "qcom,sa8155p-rpmhpd"; >> }; >> + >> +&videocc { >> + power-domains = <&rpmhpd SA8155P_CX>; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi >> index a35c0852b5a1..6573c907d7e2 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi >> @@ -14,6 +14,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -3715,6 +3716,18 @@ usb_2_dwc3: usb@a800000 { >> }; >> }; >> >> + videocc: clock-controller@ab00000 { >> + compatible = "qcom,sm8150-videocc"; >> + reg = <0 0x0ab00000 0 0x10000>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_VIDEO_AHB_CLK>; >> + power-domains = <&rpmhpd SM8150_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; > Should not be necessary anymore. Whenever the rail is turned on, we want to keep it in low_svs state instead of retention, hence added this property , please let me know why you think it is not needed? >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> camnoc_virt: interconnect@ac00000 { >> compatible = "qcom,sm8150-camnoc-virt"; >> reg = <0 0x0ac00000 0 0x1000>; >> >> -- >> 2.25.1 >> >> >