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Subject: Re: [PATCH v9 00/10] Support Andes PMU extension
From: patchwork-bot+linux-riscv@kernel.org
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 <171041943194.26728.3807889559884607630.git-patchwork-notify@kernel.org>
Date: Thu, 14 Mar 2024 12:30:31 +0000
References: <20240222083946.3977135-1-peterlin@andestech.com>
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To: Yu Chien Peter Lin <peterlin@andestech.com>
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Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Thu, 22 Feb 2024 16:39:36 +0800 you wrote:
> Hi All,
> 
> This patch series introduces the Andes PMU extension, which serves the
> same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
> is assigned to bit 18 in the custom S-mode local interrupt enable and
> pending registers (slie/slip), while the interrupt cause is (256 + 18).
> 
> [...]

Here is the summary with links:
  - [v9,01/10] riscv: errata: Rename defines for Andes
    https://git.kernel.org/riscv/c/be5e8872b3fb
  - [v9,02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
    https://git.kernel.org/riscv/c/96303bcb401c
  - [v9,03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
    https://git.kernel.org/riscv/c/f4cc33e78ba8
  - [v9,04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string
    https://git.kernel.org/riscv/c/b88727d554f0
  - [v9,05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
    https://git.kernel.org/riscv/c/95113bb70515
  - [v9,06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
    https://git.kernel.org/riscv/c/ea0e0178e101
  - [v9,07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling
    https://git.kernel.org/riscv/c/bc969d6cc96a
  - [v9,08/10] dt-bindings: riscv: Add Andes PMU extension description
    https://git.kernel.org/riscv/c/61609bf2b29d
  - [v9,09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
    https://git.kernel.org/riscv/c/270fc77e7b0e
  - [v9,10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events
    https://git.kernel.org/riscv/c/f5102e31c209

You are awesome, thank you!
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