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[209.85.219.169]) by smtp.gmail.com with ESMTPSA id n24-20020a81af18000000b0060a1f3267e2sm304151ywh.42.2024.03.14.07.48.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Mar 2024 07:48:57 -0700 (PDT) Received: by mail-yb1-f169.google.com with SMTP id 3f1490d57ef6-dcc71031680so899539276.2; Thu, 14 Mar 2024 07:48:56 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCWLIWFSzdC2sP4gsAGESJOK/0e9Wh2oUJlmYQ5zy7czjRQ0XiHbivyaqIEAvo/zETS8LPD6/eRpBMn/D+SadzSJSfuHN8tlPrkLZhPi8tgPzg1JI1FfS2aE3koKD1NiZdSgTvuoTQEe X-Received: by 2002:a5b:912:0:b0:dc6:d093:8622 with SMTP id a18-20020a5b0912000000b00dc6d0938622mr1759963ybq.15.1710427736622; Thu, 14 Mar 2024 07:48:56 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <898aa0925a9598d44721d00145015b215434cb3b.1710414195.git.geert@linux-m68k.org> <695ebdde-3dc3-41b1-b20b-f02c4ba1ae5d@sifive.com> In-Reply-To: <695ebdde-3dc3-41b1-b20b-f02c4ba1ae5d@sifive.com> From: Geert Uytterhoeven Date: Thu, 14 Mar 2024 15:48:45 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] clk: starfive: jh7100: Use provided clocks instead of hardcoded names To: Samuel Holland Cc: Albert Ou , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Paul Walmsley , Palmer Dabbelt , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Samuel, On Thu, Mar 14, 2024 at 3:32=E2=80=AFPM Samuel Holland wrote: > On 2024-03-14 6:05 AM, Geert Uytterhoeven wrote: > > The Starfive JH7100 clock driver does not use the DT "clocks" property > > to find its external input clocks, but instead relies on the names of > > the actual external clock providers. This is fragile, and caused > > breakage when sanitizing clock names in DT. > > > > Fix this by obtaining the external input clocks through the DT "clocks" > > property, and using their clk_hw objects or corresponding name. > > > > Fixes: f03606470886 ("riscv: dts: starfive: replace underscores in node= names") > > Fixes: 4210be668a09ee20 ("clk: starfive: Add JH7100 clock generator dri= ver") > > Signed-off-by: Geert Uytterhoeven > > --- a/drivers/clk/starfive/clk-starfive-jh7100.c > > +++ b/drivers/clk/starfive/clk-starfive-jh7100.c > > @@ -298,13 +311,23 @@ static int __init clk_starfive_jh7100_probe(struc= t platform_device *pdev) > > if (IS_ERR(priv->base)) > > return PTR_ERR(priv->base); > > > > + for (idx =3D 0; idx < EXT_NUM_CLKS; idx++) { > > + clk =3D devm_clk_get(&pdev->dev, jh7100_ext_clk[idx]); > > + if (IS_ERR(clk)) > > + return PTR_ERR(clk); > > + > > + priv->ext[idx] =3D __clk_get_hw(clk); > > + } > > + > > + osc_sys =3D clk_hw_get_name(priv->ext[EXT_CLK_OSC_SYS]); > > + > > priv->pll[0] =3D devm_clk_hw_register_fixed_factor(priv->dev, "pl= l0_out", > > - "osc_sys", 0, 40= , 1); > > + osc_sys, 0, 40, = 1); > > if (IS_ERR(priv->pll[0])) > > return PTR_ERR(priv->pll[0]); > > > > priv->pll[1] =3D devm_clk_hw_register_fixed_factor(priv->dev, "pl= l1_out", > > - "osc_sys", 0, 64= , 1); > > + osc_sys, 0, 64, = 1); > > These should use devm_clk_hw_register_fixed_factor_parent_hw(). (Or you c= ould Thanks, I didn't know about that function! > define a devm_clk_hw_register_fixed_factor_fw_name() and drop the other c= hanges.) Sorry, I don't understand what you mean here? Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds