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[209.85.128.182]) by smtp.gmail.com with ESMTPSA id j67-20020a819246000000b0060a588c41a3sm324357ywg.76.2024.03.14.08.59.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Mar 2024 08:59:58 -0700 (PDT) Received: by mail-yw1-f182.google.com with SMTP id 00721157ae682-60cbcd04de9so12467337b3.2; Thu, 14 Mar 2024 08:59:57 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCWnlkm4XdlilXZxjSXARM3ofp5jQnCie+0lK5i8/Pplg0JT4SODl6KTMA4jjRv4MPNCnvDo0EkQRksPl/I2eZv4UEeTTI7JmzfT0XQ6uBnGUzwQ5fC0dAHxGHvU3yzeAbo/4gBWmpMwYRUEj1F56xBZbabPkh8TTOXukIP35vR0pJ3b7MfQ4ytvZRrvR7iSAGeXVFbxpJsZAJRIee/W/MYOqhs6m71J X-Received: by 2002:a25:9801:0:b0:dc7:4ba0:9d24 with SMTP id a1-20020a259801000000b00dc74ba09d24mr1740244ybo.59.1710431997732; Thu, 14 Mar 2024 08:59:57 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240307140728.190184-1-claudiu.beznea.uj@bp.renesas.com> <20240307140728.190184-6-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20240307140728.190184-6-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 14 Mar 2024 16:59:44 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 05/10] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S To: Claudiu Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Mar 7, 2024 at 3:07=E2=80=AFPM Claudiu w= rote: > From: Claudiu Beznea > > The driver will be modified (in the next commits) to be able to specify > individual power domain ID for each IP. The driver will still > support #power-domain-cells =3D <0>, thus, previous users are not > affected. > > The #power-domain-cells =3D <1> has been instantiated only for RZ/G3S at > the moment as individual platform clock drivers need to be adapted for > this to be supported on the rest of the SoCs. > > Also, the description for #power-domain-cells was updated with the links > to per-SoC power domain IDs. > > Signed-off-by: Claudiu Beznea > --- > > Changes in v2: > - updated patch title and description > - kept both 0 and 1 for #power-domain-cells as not all the drivers, > device trees are adpated with this series > - added a reference to dt-bindings/clock/r9a0*-cpg.h for power domain > specifiers > - dropped the changes from examples section Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds