Received-SPF: pass (google.com: domain of linux-kernel+bounces-103587-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1;
Message-ID: <69a8c14c-109a-103a-b8dc-d8e303c0f0d5@quicinc.com>
Date: Thu, 14 Mar 2024 22:13:59 +0530
Precedence: bulk
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101
 Thunderbird/102.13.0
Subject: Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add qfprom node
To: Konrad Dybcio <konrad.dybcio@linaro.org>, <andersson@kernel.org>,
        <robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>
CC: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <1709727995-19821-1-git-send-email-quic_mojha@quicinc.com>
 <1709727995-19821-2-git-send-email-quic_mojha@quicinc.com>
 <45fcf8fb-9d9b-4e6a-a7c5-9bfb96875e64@linaro.org>
Content-Language: en-US
From: Mukesh Ojha <quic_mojha@quicinc.com>
In-Reply-To: <45fcf8fb-9d9b-4e6a-a7c5-9bfb96875e64@linaro.org>
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 8bit

Sorry for the late reply, was on vacation.

On 3/6/2024 9:24 PM, Konrad Dybcio wrote:
> 
> 
> On 3/6/24 13:26, Mukesh Ojha wrote:
>> Add the qfprom node for sm8450 SoC.
>>
>> Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi 
>> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index b86be34a912b..02089a388d03 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -4575,6 +4575,13 @@
>>               };
>>           };
>> +        qfprom: efuse@221c8000 {
>> +            compatible = "qcom,sm8450-qfprom", "qcom,qfprom";
>> +            reg = <0 0x221c8000 0 0x1000>;
> 
> Is is really only 0x1000-long? Also, is the base you put
> here the ECC-corrected part (if that still exists)?

No, its not.

Entire fuse space is this.
0x221C0000-0x221Cbfff

ECC corrected range is this 0x221C2000-0x221C3fff and High level OS
does have a access to ECC range however, they are not recommended for
SW usage.

Above mentioned SW range(4) in the patch is  one and only accessible 
range available out of 0-7 SW ranges(0x221C4000-0x221Cbfff with each
size 0x1000) and does not have ECC fuses.

All the downstream use cases are getting fulfilled with this.

-Mukesh

> 
> Konrad