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Message-ID: <cb19954a-5f4e-4c39-8944-5f02d3221d79@gmail.com>
Date: Wed, 13 Mar 2024 18:25:34 +0800
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Subject: Re: [PATCH v6 3/3] pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO
 driver
To: Dan Carpenter <dan.carpenter@linaro.org>
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
 krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
 p.zabel@pengutronix.de, j.neuschaefer@gmx.net,
 linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
 ychuang3@nuvoton.com, schung@nuvoton.com
References: <20240313035719.768469-1-ychuang570808@gmail.com>
 <20240313035719.768469-4-ychuang570808@gmail.com>
 <5c555723-1731-40cc-b9be-a88ef617e09f@moroto.mountain>
Content-Language: en-US
From: Jacky Huang <ychuang570808@gmail.com>
In-Reply-To: <5c555723-1731-40cc-b9be-a88ef617e09f@moroto.mountain>
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On 2024/3/13 下午 04:04, Dan Carpenter wrote:
> On Wed, Mar 13, 2024 at 03:57:19AM +0000, Jacky Huang wrote:
>> +static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl)
>> +{
>> +	struct ma35_pin_ctrl *ctrl = npctl->ctrl;
>> +	struct ma35_pin_bank *bank = ctrl->pin_banks;
>> +	int ret;
>> +	int i;
>> +
>> +	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
>> +		if (!bank->valid) {
>> +			dev_warn(&pdev->dev, "bank %s is not valid\n",
>> +				 bank->np->name);
>> +			continue;
>> +		}
>> +		bank->irqtype = 0;
>> +		bank->irqinten = 0;
>> +		bank->chip.label = bank->name;
>> +		bank->chip.of_gpio_n_cells = 2;
>> +		bank->chip.parent = &pdev->dev;
>> +		bank->chip.request = ma35_gpio_core_to_request;
>> +		bank->chip.direction_input = ma35_gpio_core_direction_in;
>> +		bank->chip.direction_output = ma35_gpio_core_direction_out;
>> +		bank->chip.get = ma35_gpio_core_get;
>> +		bank->chip.set = ma35_gpio_core_set;
>> +		bank->chip.base = -1;
>> +		bank->chip.ngpio = bank->nr_pins;
>> +		bank->chip.can_sleep = false;
>> +		spin_lock_init(&bank->lock);
>> +
>> +		if (bank->irq > 0) {
>> +			struct gpio_irq_chip *girq;
>> +
>> +			girq = &bank->chip.irq;
>> +			gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip);
>> +			girq->parent_handler = ma35_irq_demux_intgroup;
>> +			girq->num_parents = 1;
>> +
>> +			girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
>> +						     GFP_KERNEL);
>> +			if (!girq->parents)
>> +				return -ENOMEM;
> ret = -ENOMEM;
> goto fail;
>
> regards,
> dan carpenter

Thanks, I will fix it.

>> +
>> +			girq->parents[0] = bank->irq;
>> +			girq->default_type = IRQ_TYPE_NONE;
>> +			girq->handler = handle_level_irq;
>> +		}
>> +
>> +		ret = gpiochip_add_data(&bank->chip, bank);
>> +		if (ret) {
>> +			dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
>> +				bank->chip.label, ret);
>> +			goto fail;
>> +		}
>> +	}
>> +	return 0;
>> +
>> +fail:
>> +	for (--i, --bank; i >= 0; --i, --bank) {
>> +		if (!bank->valid)
>> +			continue;
>> +		gpiochip_remove(&bank->chip);
>> +	}
>> +	return ret;
>> +}

Best Regards,
Jacky Huang