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From: JeeHeng Sia <jeeheng.sia@starfivetech.com>
To: Samuel Holland <samuel.holland@sifive.com>, Palmer Dabbelt
	<palmer@dabbelt.com>, "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>
CC: Albert Ou <aou@eecs.berkeley.edu>, Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>, Leyfoon Tan
	<leyfoon.tan@starfivetech.com>, Paul Walmsley <paul.walmsley@sifive.com>,
	Pavel Machek <pavel@ucw.cz>, "Rafael J. Wysocki" <rafael@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>
Subject: RE: [PATCH] riscv: Do not save the scratch CSR during suspend
Thread-Topic: [PATCH] riscv: Do not save the scratch CSR during suspend
Thread-Index: AQHadLdqgBiYlFfag0upukB5n1Ud1rE4QBkA
Date: Fri, 15 Mar 2024 04:55:57 +0000
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> -----Original Message-----
> From: Samuel Holland <samuel.holland@sifive.com>
> Sent: Wednesday, March 13, 2024 3:57 AM
> To: Palmer Dabbelt <palmer@dabbelt.com>; linux-riscv@lists.infradead.org
> Cc: Samuel Holland <samuel.holland@sifive.com>; Albert Ou <aou@eecs.berke=
ley.edu>; Andrew Jones <ajones@ventanamicro.com>;
> Conor Dooley <conor.dooley@microchip.com>; Leyfoon Tan <leyfoon.tan@starf=
ivetech.com>; Paul Walmsley
> <paul.walmsley@sifive.com>; Pavel Machek <pavel@ucw.cz>; Rafael J. Wysock=
i <rafael@kernel.org>; JeeHeng Sia
> <jeeheng.sia@starfivetech.com>; linux-kernel@vger.kernel.org; linux-pm@vg=
er.kernel.org
> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
>=20
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
>=20
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>=20
>  arch/riscv/include/asm/suspend.h | 1 -
>  arch/riscv/kernel/suspend.c      | 3 +--
>  2 files changed, 1 insertion(+), 3 deletions(-)
>=20
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/su=
spend.h
> index 491296a335d0..6569eefacf38 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -13,7 +13,6 @@ struct suspend_context {
>  	/* Saved and restored by low-level functions */
>  	struct pt_regs regs;
>  	/* Saved and restored by high-level functions */
> -	unsigned long scratch;
>  	unsigned long envcfg;
>  	unsigned long tvec;
>  	unsigned long ie;
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index 299795341e8a..3d306d8a253d 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -14,7 +14,6 @@
>=20
>  void suspend_save_csrs(struct suspend_context *context)
>  {
> -	context->scratch =3D csr_read(CSR_SCRATCH);
>  	if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_=
XLINUXENVCFG))
>  		context->envcfg =3D csr_read(CSR_ENVCFG);
>  	context->tvec =3D csr_read(CSR_TVEC);
> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
>=20
>  void suspend_restore_csrs(struct suspend_context *context)
>  {
> -	csr_write(CSR_SCRATCH, context->scratch);
> +	csr_write(CSR_SCRATCH, 0);
If the register is always zero, do we need to explicitly write zero to the =
register during resume?
>  	if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_=
XLINUXENVCFG))
>  		csr_write(CSR_ENVCFG, context->envcfg);
>  	csr_write(CSR_TVEC, context->tvec);
> --
> 2.43.1