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Fri, 15 Mar 2024 10:26:43 -0700 (PDT) Message-ID: <94e3d09a-e6a4-4808-bc29-3f494b65e170@gmail.com> Date: Fri, 15 Mar 2024 10:26:41 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] arm64: dts: mediatek: mt7622: set PHY address of MT7531 switch to 0x1f Content-Language: en-US To: arinc.unal@arinc9.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: mithat.guner@xeront.com, erkin.bozoglu@xeront.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org References: <20240314-for-mediatek-mt7531-phy-address-v1-0-52f58db01acd@arinc9.com> <20240314-for-mediatek-mt7531-phy-address-v1-1-52f58db01acd@arinc9.com> From: Florian Fainelli In-Reply-To: <20240314-for-mediatek-mt7531-phy-address-v1-1-52f58db01acd@arinc9.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 3/14/24 05:20, Arınç ÜNAL via B4 Relay wrote: > From: Arınç ÜNAL > > The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two > findings that support this. There's no bootstrapping option to change the > PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY > address of the switch. So the reg property on the device tree is currently > ignored by the Linux driver. > > Therefore, describe the correct PHY address on boards that have this > switch. Can we call it a pseudo PHY to use a similar terminology as what is done through drivers/net/dsa/{bcm_sf2,b53}*? This is not a real PHY as in it has no actual transceiver/digital signal processing logic, this is a piece of logic that snoops for MDIO transactions at that specific address and lets you access the switch's internal register as if it was a MDIO device. LGTM otherwise! -- Florian