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Message-ID: <0fda46c7-87e1-41f1-b3f0-ee3d1a4ac601@wanadoo.fr>
Date: Sat, 16 Mar 2024 15:03:13 +0100
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Subject: Re: [PATCH V2] irqchip/loongson-pch-pic: Update interrupt
 registration policy
Content-Language: en-MW, en-GB
To: Tianyang Zhang <zhangtianyang@loongson.cn>, chenhuacai@kernel.org,
 jiaxun.yang@flygoat.com, tglx@linutronix.de
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
 Baoqi Zhang <zhangbaoqi@loongson.cn>, Biao Dong <dongbiao@loongson.cn>
References: <20240316082141.26139-1-zhangtianyang@loongson.cn>
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
In-Reply-To: <20240316082141.26139-1-zhangtianyang@loongson.cn>
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Le 16/03/2024 à 09:21, Tianyang Zhang a écrit :
> From: Baoqi Zhang <zhangbaoqi@loongson.cn>
> 
> This patch remove the fixed mapping between the 7A interrupt source
> and the HT interrupt vector, and replaced it with a dynamically
> allocated approach.
> 
> We introduce a mapping table in struct pch_pic, where each interrupt
> source will allocate an index as a 'hwirq' from the table in the order
> of application and set table value as interrupt source number. This hwirq
> will be configured as its vector in the HT interrupt controller. For an
> interrupt source, the validity period of the obtained hwirq will last until
> the system reset
> 
> This will be more conducive to fully utilizing existing vectors to
> support more devices
> 
> Signed-off-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
> Signed-off-by: Biao Dong <dongbiao@loongson.cn>
> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
> ---
>   drivers/irqchip/irq-loongson-pch-pic.c | 77 ++++++++++++++++++++------
>   1 file changed, 59 insertions(+), 18 deletions(-)
> 

..

> @@ -171,6 +183,27 @@ static int pch_pic_domain_translate(struct irq_domain *d,
>   			return -EINVAL;
>   
>   		*hwirq = fwspec->param[0] - priv->gsi_base;
> +
> +		raw_spin_lock_irqsave(&priv->pic_lock, flags);
> +		/* Check pic-table to confirm if the hwirq has been assigned */
> +		for (i = 0; i < priv->inuse; i++) {
> +			if (priv->table[i] == *hwirq) {
> +				*hwirq = i;
> +				break;
> +			}
> +		}
> +		if (i == priv->inuse) {
> +			/* Assign a new hwirq in pic-table */
> +			if (priv->inuse >= PIC_COUNT) {
> +				pr_err("pch-pic domain has no free vectors\n");
> +				raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
> +				return -EINVAL;
> +			}
> +			priv->table[priv->inuse] = *hwirq;
> +			*hwirq = priv->inuse++;
> +		}
> +		raw_spin_unlock_irqrestore(&priv->pic_lock, flags);

Hi,

not sure if it helps or if this is a hot path, but, IIUC, taking the 
lock could be avoided with some code reordering and 'inuse' being an 
atomic_t.

IIUC, the lock is only needed to protect 'inuse' and 'table' is never 
modified afterwards.

Somehing like:

 > +		int cur_inuse;
		...
 > +		cur_inuse = atomic_read(&priv->inuse);
 > +		/* Check pic-table to confirm if the hwirq has been assigned */
 > +		for (i = 0; i < cur_inuse; i++) {
 > +			if (priv->table[i] == *hwirq) {
 > +				*hwirq = i;
 > +				break;
 > +			}
 > +		}
 > +		if (i == cur_inuse) {
 > +			/* Assign a new hwirq in pic-table */
 > +			if (cur_inuse >= PIC_COUNT) {
 > +				pr_err("pch-pic domain has no free vectors\n");
 > +				return -EINVAL;
 > +			}
 > +			priv->table[cur_inuse] = *hwirq;
 > +			*hwirq = atomic_inc_return(&priv->inuse);
 > +		}


> +
>   		if (fwspec->param_count > 1)
>   			*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
>   		else
> @@ -194,6 +227,9 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
>   	if (err)
>   		return err;
>   
> +	/* Write vector ID */
> +	writeb(priv->ht_vec_base + hwirq, priv->base + PCH_INT_HTVEC(hwirq_to_bit(priv, hwirq)));
> +
>   	parent_fwspec.fwnode = domain->parent->fwnode;
>   	parent_fwspec.param_count = 1;
>   	parent_fwspec.param[0] = hwirq + priv->ht_vec_base;

..