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charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:jub8QDgSnZ8AbSgBVMW8uke/xMwe9dhFq6FVCojQ8aQHsYD5xYe 57cmu43IYbWzOV29/Z70p0cFAl1m0UJhGxktZFocGeazwdn5/qoXVRNxT/gMA3YYJMBbutd Yiz68XaOVZACJ1WA216mIwJDnGJXJAF7j0OEVYLlooR1Iioj3GLQolceZ4jPPIN6qx7zcol QDgqRuRxVGBgwpCQQcf0w== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:TIF9uqa/PxY=;6PRj0Lq0EZp9bJwDP99uvSFDlZM SV13KTGpVXH7plqQz1K1PxEhcvGYUk9dFFaA9rhtE8ThE2BL21RrBB9eGHlhaF1ufG5h7SuIb A73Bkhg8wBm+OkBbu8kTy2gY5op83w8KOuyO9pRjEN+FWHj28GLzFoLzUe71Y57knzfwd+ziN De32tMBj5/liKY4VJZhYQHnUsp7RFKc6E5lQJRxYNH0hXIeq4SbmwllAnHQWW3vbCK7VoxWMt bhSttjcB+cHB+871Ka3U1HVl5GDEsenHxWHnkej69mWS5RcpuCIDoIhdn/pGntlZvpr0lantT z6/No3yXtXZZDVF0B/iWMRfnybdzglpjNhaLimHYkWxeY45uLhPJxWcpj8vhC7BfCn7EY9paL EMb42osDcjDa6bT96UwBgnB55jun21yDt8WXGhNYUFuFWJ+Ekx39D823PdpC9AIURdzKRtS4D Dg60kkGrvGcmQYS3zLqH9ocU3DXRw6Gk0F/ei99rA4QxVYWI0qVT6qqpwTF0hR3Hy6kOpHafS 7bigysWVk7iC8WsjP5eANJxtFNJgi1jZfCLsXlJqLEVoeeRU8YObYTZsMcYbmLgMnVpVSZnFh 54gfdUD4U7RHtXtGZsyYrnCnpl6bWXVy2OC5pQuNhZMnaxC9zOw3c4DmR8QHMOsa3zmdVets8 JKGyFpU3u0D5MKBpIjImOGGTuLeY7dXGWNqr5PVaQue8hvceObdLCdWY/s5TAeIdgEOQ6lfkU yPAjiGOCIuoOvPKPSoK99RUfv1kqCUEPHwelDv35Ha5SS4WJ5iDj+Nesn+3gO+2QKQyOOc9CL 1qYxP0gw4PzhpbQSfoq/SJ+umz3zkmvnwMqUNWaiXVbFE= Hi Andrea, Am 13.03.24 um 15:08 schrieb Andrea della Porta: > From: Phil Elwell > > Add the ability to interpret the high bits of the dreq specifier as > flags to be included in the DMA_CS register. The motivation for this > change is the ability to set the DISDEBUG flag for SD card transfers > to avoid corruption when using the VPU debugger. AFAIK this and the following 2 patches also requires modification on the DT side. So either they must be included in the series or we better leave them out completely. I'm not sure which one are really necessary for 40 bit support. Regards > > Signed-off-by: Phil Elwell > Signed-off-by: Andrea della Porta > --- > drivers/dma/bcm2835-dma.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c > index 428253b468ac..3d9973dd041d 100644 > --- a/drivers/dma/bcm2835-dma.c > +++ b/drivers/dma/bcm2835-dma.c > @@ -137,6 +137,10 @@ struct bcm2835_desc { > #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ > #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 *= / > #define BCM2835_DMA_BURST_LENGTH(x) (((x) & 15) << 12) > +#define BCM2835_DMA_CS_FLAGS(x) ((x) & (BCM2835_DMA_PRIORITY(15) | \ > + BCM2835_DMA_PANIC_PRIORITY(15) | \ > + BCM2835_DMA_WAIT_FOR_WRITES | \ > + BCM2835_DMA_DIS_DEBUG)) > #define BCM2835_DMA_PER_MAP(x) (((x) & 31) << 16) /* REQ source */ > #define BCM2835_DMA_WAIT(x) (((x) & 31) << 21) /* add DMA-wait cycles = */ > #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts *= / > @@ -449,7 +453,8 @@ static void bcm2835_dma_start_desc(struct bcm2835_ch= an *c) > c->desc =3D to_bcm2835_dma_desc(&vd->tx); > > writel(c->desc->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); > - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); > + writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), > + c->chan_base + BCM2835_DMA_CS); > } > > static irqreturn_t bcm2835_dma_callback(int irq, void *data) > @@ -476,7 +481,8 @@ static irqreturn_t bcm2835_dma_callback(int irq, voi= d *data) > * if this IRQ handler is threaded.) If the channel is finished, it > * will remain idle despite the ACTIVE flag being set. > */ > - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, > + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | > + BCM2835_DMA_CS_FLAGS(c->dreq), > c->chan_base + BCM2835_DMA_CS); > > d =3D c->desc;