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Date: Sun, 17 Mar 2024 20:31:51 -0500
From: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, 
	Joerg Roedel <joro@8bytes.org>, Rob Herring <robh@kernel.org>, 
	Marijn Suijten <marijn.suijten@somainline.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, 
	Johan Hovold <johan+linaro@kernel.org>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: sc8280xp: Describe the PCIe
 SMMUv3
Message-ID: <phledylmdu23yrw6f4x7fkefntrejuwagazebsnkgyxsweodzg@pddhnc2gwexz>
References: <20231219-topic-8280_smmuv3-v2-0-c67bd3226687@linaro.org>
 <20231219-topic-8280_smmuv3-v2-2-c67bd3226687@linaro.org>
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In-Reply-To: <20231219-topic-8280_smmuv3-v2-2-c67bd3226687@linaro.org>

On Sat, Mar 09, 2024 at 02:31:10PM +0100, Konrad Dybcio wrote:
> SC8280XP actually has a third SMMU, which can be seen in e.g. the IORT
> ACPI table and is used for the PCIe hosts.
> 
> Unfortunately though, the secure firmware seems to be configured in a
> way such that Linux can't touch it, not even read back the ID registers.
> It also seems like the SMMU is configured to run in some sort of bypass
> mode, completely opaque to the OS.
> 
> Describe it so that one can configure it when running Linux as a
> hypervisor (e.g with [1]) and for hardware description completeness.
> 
> [1] https://github.com/TravMurav/slbounce
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Have this information been validated? Or are you suggesting we add it
for documentation purposes?

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index a5b194813079..28edd30a9c04 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4648,6 +4648,22 @@ cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
>  			};
>  		};
>  
> +		pcie_smmu: iommu@14f80000 {
> +			compatible = "qcom,sc8280xp-smmu-v3", "arm,smmu-v3";
> +			reg = <0 0x14f80000 0 0x80000>;
> +			interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "eventq",
> +					  "gerror",
> +					  "cmdq-sync";
> +			#iommu-cells = <1>;
> +			dma-coherent;
> +
> +			/* The hypervisor prevents register access from Linux */
> +			status = "reserved";
> +		};
> +
>  		apps_smmu: iommu@15000000 {
>  			compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
>  			reg = <0 0x15000000 0 0x100000>;
> 
> -- 
> 2.44.0
>