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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Mon, 18 Mar 2024 10:11:37 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 18 Mar 2024 05:11:33 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v6 2/6] cpufreq: amd-pstate: initialize new core precision boost state Date: Mon, 18 Mar 2024 18:11:09 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|DM4PR12MB6424:EE_ X-MS-Office365-Filtering-Correlation-Id: c76b125a-38da-4c3e-4125-08dc4733cc11 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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If core performance boost is disabled while a core is in a boosted P-state, the core transitions to the highest performance non-boosted P-state, that is the same as the nominal frequency limit. Reported-by: Artem S. Tashkinov" Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 39 +++++++++++++++++++++++++++--------- include/linux/amd-pstate.h | 13 ++++++++++++ 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 59a2db225d98..81787f83c906 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -68,6 +68,8 @@ static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); /* * AMD Energy Preference Performance (EPP) @@ -665,18 +667,27 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) return 0; } -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - u32 highest_perf, nominal_perf; + u64 boost_val; + int ret; - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); + return ret; + } - if (highest_perf <= nominal_perf) - return; + amd_pstate_global_params.cpb_supported = !(boost_val & MSR_K7_HWCR_CPB_DIS); + + if (amd_pstate_global_params.cpb_supported) { + cpudata->boost_supported = true; + current_pstate_driver->boost_enabled = true; + } - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; + + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -900,6 +911,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) amd_pstate_init_prefcore(cpudata); + /* initialize cpu cores boot state */ + ret = amd_pstate_boost_init(cpudata); + if (ret) + goto free_cpudata1; + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -956,7 +972,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1363,6 +1378,11 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) amd_pstate_init_prefcore(cpudata); + /* initialize cpu cores boot state */ + ret = amd_pstate_boost_init(cpudata); + if (ret) + goto free_cpudata1; + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1417,7 +1437,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 6b832153a126..c5e41de65f70 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -134,4 +134,17 @@ struct quirk_entry { u32 lowest_freq; }; +/** + * struct amd_pstate_global_params - Global parameters, mostly tunable via sysfs. + * @cpb_boost: Whether or not to use boost CPU P-states. + * @cpb_supported: Whether or not CPU boost P-states are available + * based on the MSR_K7_HWCR bit[25] state + */ +struct amd_pstate_global_params { + bool cpb_boost; + bool cpb_supported; +}; + +extern struct amd_pstate_global_params amd_pstate_global_params; + #endif /* _LINUX_AMD_PSTATE_H */ -- 2.34.1