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From: Thomas Gleixner <tglx@linutronix.de>
To: Christophe JAILLET <christophe.jaillet@wanadoo.fr>, Tianyang Zhang
 <zhangtianyang@loongson.cn>, chenhuacai@kernel.org,
 jiaxun.yang@flygoat.com
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Baoqi Zhang
 <zhangbaoqi@loongson.cn>, Biao Dong <dongbiao@loongson.cn>
Subject: Re: [PATCH V2] irqchip/loongson-pch-pic: Update interrupt
 registration policy
In-Reply-To: <0fda46c7-87e1-41f1-b3f0-ee3d1a4ac601@wanadoo.fr>
References: <20240316082141.26139-1-zhangtianyang@loongson.cn>
 <0fda46c7-87e1-41f1-b3f0-ee3d1a4ac601@wanadoo.fr>
Date: Mon, 18 Mar 2024 12:18:25 +0100
Message-ID: <87wmpziy9q.ffs@tglx>
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On Sat, Mar 16 2024 at 15:03, Christophe JAILLET wrote:
> Le 16/03/2024 =C3=A0 09:21, Tianyang Zhang a =C3=A9crit=C2=A0:
>> @@ -171,6 +183,27 @@ static int pch_pic_domain_translate(struct irq_doma=
in *d,
>>   			return -EINVAL;
>>=20=20=20
>>   		*hwirq =3D fwspec->param[0] - priv->gsi_base;
>> +
>> +		raw_spin_lock_irqsave(&priv->pic_lock, flags);
>> +		/* Check pic-table to confirm if the hwirq has been assigned */
>> +		for (i =3D 0; i < priv->inuse; i++) {
>> +			if (priv->table[i] =3D=3D *hwirq) {
>> +				*hwirq =3D i;
>> +				break;
>> +			}
>> +		}
>> +		if (i =3D=3D priv->inuse) {
>> +			/* Assign a new hwirq in pic-table */
>> +			if (priv->inuse >=3D PIC_COUNT) {
>> +				pr_err("pch-pic domain has no free vectors\n");
>> +				raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
>> +				return -EINVAL;
>> +			}
>> +			priv->table[priv->inuse] =3D *hwirq;
>> +			*hwirq =3D priv->inuse++;
>> +		}
>> +		raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
>
> Hi,
>
> not sure if it helps or if this is a hot path, but, IIUC, taking the=20
> lock could be avoided with some code reordering and 'inuse' being an=20
> atomic_t.

It's the translate and setup path, so nothing to optimize here.