Received-SPF: pass (google.com: domain of linux-kernel+bounces-106085-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Date: Mon, 18 Mar 2024 11:43:19 +0000
From: Conor Dooley <conor@kernel.org>
To: Qingfang Deng <dqfext@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Heiko Stuebner <heiko@sntech.de>, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Qingfang Deng <qingfang.deng@siflower.com.cn>
Subject: Re: [PATCH v2] perf: RISC-V: fix IRQ detection on T-Head C908
Message-ID: <20240318-spoilage-drastic-d58a16c8b9f3@spud>
References: <20240318100241.267857-1-dqfext@gmail.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
	protocol="application/pgp-signature"; boundary="ji7VlNa0+B9+NsUi"
Content-Disposition: inline
In-Reply-To: <20240318100241.267857-1-dqfext@gmail.com>


--ji7VlNa0+B9+NsUi
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Mon, Mar 18, 2024 at 06:02:40PM +0800, Qingfang Deng wrote:
> From: Qingfang Deng <qingfang.deng@siflower.com.cn>
>=20
> T-Head C908 has the same IRQ num and CSR as previous C9xx cores, but
> reports non-zero marchid and mimpid. Add the check for C908 ID.
>=20
> Fixes: 65e9fb081877 ("drivers/perf: riscv_pmu_sbi: add support for PMU va=
riant on T-Head C9xx cores")
> Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
> ---
> v2: add C908 ID check

If you read the replies to v1 in full, you would see I objected there to
this approach and made suggestions as to how I would like it done:
https://lore.kernel.org/linux-riscv/IA1PR20MB4953CEBE4CB6AC7238849353BB282@=
IA1PR20MB4953.namprd20.prod.outlook.com/

I don't want to see an expansion of these ID checks.

Thanks,
Conor.
>=20
>  arch/riscv/errata/thead/errata.c       | 5 +++--
>  arch/riscv/include/asm/vendorid_list.h | 2 ++
>  drivers/perf/riscv_pmu_sbi.c           | 6 ++++--
>  3 files changed, 9 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/e=
rrata.c
> index b1c410bbc1ae..da3b34866d8f 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -125,8 +125,9 @@ static bool errata_probe_pmu(unsigned int stage,
>  	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
>  		return false;
> =20
> -	/* target-c9xx cores report arch_id and impid as 0 */
> -	if (arch_id !=3D 0 || impid !=3D 0)
> +	/* Early c9xx cores report arch_id and impid as 0 */
> +	if (!((arch_id =3D=3D 0 && impid =3D=3D 0) ||
> +	      (arch_id =3D=3D THEAD_C908_ARCH_ID && impid =3D=3D THEAD_C908_IMP=
_ID)))
>  		return false;
> =20
>  	if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT)
> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/=
asm/vendorid_list.h
> index 2f2bb0c84f9a..57b3de510d38 100644
> --- a/arch/riscv/include/asm/vendorid_list.h
> +++ b/arch/riscv/include/asm/vendorid_list.h
> @@ -8,5 +8,7 @@
>  #define ANDES_VENDOR_ID		0x31e
>  #define SIFIVE_VENDOR_ID	0x489
>  #define THEAD_VENDOR_ID		0x5b7
> +#define  THEAD_C908_ARCH_ID	0x8000000009140d00
> +#define  THEAD_C908_IMP_ID	0x8a000
> =20
>  #endif
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index bbd6fe021b3a..34d8689982de 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -833,8 +833,10 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu,=
 struct platform_device *pde
>  		riscv_pmu_use_irq =3D true;
>  	} else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
>  		   riscv_cached_mvendorid(0) =3D=3D THEAD_VENDOR_ID &&
> -		   riscv_cached_marchid(0) =3D=3D 0 &&
> -		   riscv_cached_mimpid(0) =3D=3D 0) {
> +		   ((riscv_cached_marchid(0) =3D=3D 0 &&
> +		     riscv_cached_mimpid(0) =3D=3D 0) ||
> +		    (riscv_cached_marchid(0) =3D=3D THEAD_C908_ARCH_ID &&
> +		     riscv_cached_mimpid(0) =3D=3D THEAD_C908_IMP_ID))) {
>  		riscv_pmu_irq_num =3D THEAD_C9XX_RV_IRQ_PMU;
>  		riscv_pmu_use_irq =3D true;
>  	} else if (riscv_isa_extension_available(NULL, XANDESPMU) &&
> --=20
> 2.34.1
>=20
>=20

--ji7VlNa0+B9+NsUi
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZfgo1wAKCRB4tDGHoIJi
0rEaAQDKUky9LX6dqR7EomEioJbyQIe8qlZhpz+Ik+MYkuLzvwD/cjp4nP0ALNBb
riWgQLQSodPaZRnnTJtbjk2WoMH6Igw=
=LZNq
-----END PGP SIGNATURE-----

--ji7VlNa0+B9+NsUi--