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From: Prabhakar <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Chris Brandt <chris.brandt@renesas.com>,
	Magnus Damm <magnus.damm@gmail.com>
Cc: linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 2/2] clocksource/drivers/renesas-ostm: Add OSTM support for RZ/V2H(P) SoC
Date: Mon, 18 Mar 2024 16:07:31 +0000
Message-Id: <20240318160731.33960-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20240318160731.33960-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

RZ/V2H(P) (R9A09G057) SoC has Generic Timer Module(a.k.a OSTM) which
needs to deassert the reset line before accessing any registers just
like the RZ/G2L SoC.

Enable the entry point for RZ/V2H(P) SoC so that we can deassert
the reset line in probe callback.

While at it use IS_ENABLED() macro instead of open coding.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clocksource/renesas-ostm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c
index 8da972dc1713..b8b3c82b2528 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -224,7 +224,7 @@ static int __init ostm_init(struct device_node *np)
 
 TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
 
-#ifdef CONFIG_ARCH_RZG2L
+#if IS_ENABLED(CONFIG_ARCH_RZG2L) || IS_ENABLED(CONFIG_ARCH_R9A09G057)
 static int __init ostm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-- 
2.34.1