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Date: Mon, 18 Mar 2024 15:46:54 -0700
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Subject: Re: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908
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To: Andrew Jones <ajones@ventanamicro.com>,
 Inochi Amaoto <inochiama@outlook.com>
Cc: Conor Dooley <conor@kernel.org>, Qingfang Deng <dqfext@gmail.com>,
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From: Atish Patra <atishp@rivosinc.com>
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On 3/15/24 01:11, Andrew Jones wrote:
> On Wed, Mar 13, 2024 at 09:31:26AM +0800, Inochi Amaoto wrote:
> ...
>> IMHO, it may be better to use a new DT property like "riscv,cpu-errata" or
>> "<vendor>,cpu-errata". It can achieve almost everything like using pseudo
>> isa. And the only cost I think is a small amount code to parse this.
>>
> 
> What's the ACPI equivalent for this new DT property? If there isn't one,
> then the cost is also to introduce something to the ACPI spec and add the
> ACPI parsing code.
> 
> I'd much rather we call specified behaviors "extensions", whether they
> are vendor-specific or RVI standard, and then treat all extensions the
> same way in hardware descriptions and Linux. It'd also be best if errata
> in extension implementations were handled by replacing the extension in
> the hardware description with a new name which is specifically for the
> behavior Linux should expect. (Just because two extensions are almost the
> same doesn't mean we should say we have one and then have some second
> mechanism to say, "well, not really, instead of that, it's this". It's
> cleaner to just remove the extension it doesn't properly implement from
> its hardware description and create a name for the behavior it does have.)
> 
> Errata in behaviors which don't have extension names (are hopefully few)
> and are where mvendorid and friends would need to be checked, but then why
> not create a pseudo extension name, as Conor suggests, so the rest of
> Linux code can manage errata the same way it manages every other behavior?
> 
> The growth rate of the ISA bitmap is worth thinking about, though, since
> we have several copies of it (at least one "all harts" bitmap, one bitmap
> for each hart, another one for each vcpu, and then there's nested virt...)
> We don't have enough extensions to worry about it now, but we can
> eventually try partitioning, using common maps for common bits, not
> storing bits which can be inferred from other bits, etc.

This is my biggest worry going forward. We already have a ever growing 
standard RVI extension list. On top of that we have genuine vendor 
extensions. IMHO, errata are bit different than extensions as there will 
be few vendor extensions in the future but many hardware erratas :)
If we start calling every hardware errata as an pseudo ISA extensions, 
we will much bigger problem maintaining it in the future.

We discussed this earlier during the Andes PMU extension series[1] as 
well. We have three types of extensions in discussions now.

1. standard RVI extensions
2. Vendor extensions
	a. Genuine vendor extension
	b. Vendor erratas which can be described as pseudo-extensions now

Keeping all these within a single ISA bitmap space seems very odd to me.
I think the feasible approach would be to partition the standard and 
vendor ISA extension space as you suggested.


For 2.b, either we can start defining pseudo extensions or adding 
vendor/arch/impid checks.

@Conor: You seems to prefer the earlier approach instead of adding the 
checks. Care to elaborate why do you think that's a better method 
compared to a simple check ?


I agree that don't have the crystal ball and may be proven wrong in the 
future (I will be definitely happy about that!). But given the diversity 
of RISC-V ecosystem, I feel that may be our sad reality.


[1] 
https://lore.kernel.org/linux-riscv/20240110073917.2398826-8-peterlin@andestech.com/

> 
> Thanks,
> drew
> 
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