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Sender: Ingo Molnar <mingo.kernel.org@gmail.com>
Date: Tue, 19 Mar 2024 11:17:55 +0100
From: Ingo Molnar <mingo@kernel.org>
To: Sandipan Das <sandipan.das@amd.com>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, peterz@infradead.org, acme@kernel.org,
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Subject: Re: [PATCH v4 1/2] x86/cpufeatures: Add dedicated feature word for
 CPUID leaf 0x80000022[EAX]
Message-ID: <ZflmU+H2Lt2I0VOq@gmail.com>
References: <cover.1710836172.git.sandipan.das@amd.com>
 <846eebace0aea3a600b81b06bddd0024e5ac1350.1710836172.git.sandipan.das@amd.com>
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In-Reply-To: <846eebace0aea3a600b81b06bddd0024e5ac1350.1710836172.git.sandipan.das@amd.com>


* Sandipan Das <sandipan.das@amd.com> wrote:

> Move the existing scattered performance monitoring related feature bits
> from CPUID leaf 0x80000022[EAX] into a dedicated word since additional
> bits will be defined from the same leaf in the future. This includes
> X86_FEATURE_PERFMON_V2 and X86_FEATURE_AMD_LBR_V2.
> 
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> ---
>  arch/x86/include/asm/cpufeature.h        |  7 +++++--
>  arch/x86/include/asm/cpufeatures.h       | 10 +++++++---
>  arch/x86/include/asm/disabled-features.h |  3 ++-
>  arch/x86/include/asm/required-features.h |  3 ++-
>  arch/x86/kernel/cpu/common.c             |  3 +++
>  arch/x86/kernel/cpu/scattered.c          |  2 --
>  arch/x86/kvm/cpuid.c                     |  5 +----
>  arch/x86/kvm/reverse_cpuid.h             |  1 -
>  8 files changed, 20 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index a1273698fc43..68dd27d60748 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -33,6 +33,7 @@ enum cpuid_leafs
>  	CPUID_7_EDX,
>  	CPUID_8000_001F_EAX,
>  	CPUID_8000_0021_EAX,
> +	CPUID_8000_0022_EAX,

>  #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
>  #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
>  #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
> -#define X86_FEATURE_AMD_LBR_V2		( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
> +/* FREE!				( 3*32+17) */
>  #define X86_FEATURE_CLEAR_CPU_BUF	( 3*32+18) /* "" Clear CPU buffers using VERW */
>  #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
>  #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
> @@ -209,7 +209,7 @@
>  #define X86_FEATURE_SSBD		( 7*32+17) /* Speculative Store Bypass Disable */
>  #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
>  #define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */
> -#define X86_FEATURE_PERFMON_V2		( 7*32+20) /* AMD Performance Monitoring Version 2 */
> +/* FREE!				( 7*32+20) */
>  #define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
>  #define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */
>  #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */
> @@ -459,6 +459,10 @@
>  #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
>  #define X86_FEATURE_SRSO_NO		(20*32+29) /* "" CPU is not affected by SRSO */
>  
> +/* AMD-defined performance monitoring features, CPUID level 0x80000022 (EAX), word 21 */
> +#define X86_FEATURE_PERFMON_V2		(21*32+ 0) /* AMD Performance Monitoring Version 2 */
> +#define X86_FEATURE_AMD_LBR_V2		(21*32+ 1) /* AMD Last Branch Record Extension Version 2 */

Thank you! I presume you tested both patches on the relevant system 
with the X86_FEATURE_AMD_LBR_PMC_FREEZE bug?

Thanks,

	Ingo