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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Tue, 19 Mar 2024 12:48:45 +0000
Message-ID: <CA+V-a8tPCK_4tqeoNZ69UYJjb_Np4OpBnz9D=4+JwzE+QPUb2Q@mail.gmail.com>
Subject: Re: [PATCH v3 3/4] dt-bindings: serial: renesas,scif: Document
 R9A09G057 support
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>, 
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, linux-kernel@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-serial@vger.kernel.org, 
	linux-renesas-soc@vger.kernel.org, 
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

Thank you for the review.

On Tue, Mar 19, 2024 at 8:12=E2=80=AFAM Geert Uytterhoeven <geert@linux-m68=
k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Mar 18, 2024 at 6:22=E2=80=AFPM Prabhakar <prabhakar.csengg@gmail=
com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document support for the Serial Communication Interface with FIFO (SCIF=
)
> > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface =
in
> > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC =
has
> > three additional interrupts: one for Tx end/Rx ready and the other two =
for
> > Rx and Tx buffer full, which are edge-triggered.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > - Added SoC specific compat string
>
> Thanks for the update!
>
> > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > @@ -79,6 +79,8 @@ properties:
> >                - renesas,scif-r9a08g045      # RZ/G3S
> >            - const: renesas,scif-r9a07g044   # RZ/G2{L,LC} fallback
> >
> > +      - const: renesas,scif-r9a09g057       # RZ/V2H(P)
> > +
> >    reg:
> >      maxItems: 1
> >
> > @@ -204,6 +206,37 @@ allOf:
> >              - const: dri
> >              - const: tei
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,scif-r9a09g057
> > +    then:
> > +      properties:
> > +        interrupts:
> > +          items:
> > +            - description: Error interrupt
>
> [...]
>
> These descriptions should be at the top level.  The SoC-specific rules
> should just restrict the lower limit (interrupts/minItems).
>
I think I'm misunderstanding here. As per patch 2/4 the DT maintainer
wants properties at top level with just minItems/maxItems and have SoC
specific listed in the checks (as pointed out to me like [0])

[0] https://elixir.bootlin.com/linux/v6.8/source/Documentation/devicetree/b=
indings/ufs/qcom,ufs.yaml#L48

> > +
> > +        interrupt-names:
> > +          items:
> > +            - const: eri
>
> [...]
>
> Likewise.
>
> In addition, you should restrict clocks/maxItems to 1, as on RZ/V2H
> only the UART functional clock is supported.
>
Agreed.

Cheers,
Prabhakar