Received-SPF: pass (google.com: domain of linux-kernel+bounces-107770-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
From: Frank Li <Frank.Li@nxp.com>
Date: Tue, 19 Mar 2024 12:07:13 -0400
Subject: [PATCH v5 3/5] PCI: dwc: Add outbound MSG TLPs support
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Message-Id: <20240319-pme_msg-v5-3-af9ffe57f432@nxp.com>
References: <20240319-pme_msg-v5-0-af9ffe57f432@nxp.com>
In-Reply-To: <20240319-pme_msg-v5-0-af9ffe57f432@nxp.com>
To: Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>, 
 Gustavo Pimentel <gustavo.pimentel@synopsys.com>, 
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, 
 Lorenzo Pieralisi <lpieralisi@kernel.org>, 
 =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>, 
 Rob Herring <robh@kernel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
 Conor Dooley <conor+dt@kernel.org>, imx@lists.linux.dev
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, 
 devicetree@vger.kernel.org, Frank Li <Frank.Li@nxp.com>, 
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>, 
 Serge Semin <fancer.lancer@gmail.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?utf-8?B?dmlGeDhlNE1OWjJDeW1HMTN1eVB4UXlMSUwyeSt2QXFQemF1ZXhuTThpM2VF?=
 =?utf-8?B?OG1LMlB6K3FZZWlyU0sxOVQ3NU5iVnB4emgvR2tQNks4TXN1L0lyNHg1Ly9P?=
 =?utf-8?B?KzJmQU4zWVFwSWZ6VVJSSHd0OVo4ZURUcjJuSjd4b04wZ0JzaDZYcm42Uy9J?=
 =?utf-8?B?RmM2VkZva21sT3prVW5LRkdsRXlzN0Ixblo5dHdFSGpRQWZISVVNS1l4elIy?=
 =?utf-8?B?UThrMHJmZFN5NTF0QUlMb3ZvWUowWjN4dkd5V2toVUZ1cHBIS01oNm9tNW9l?=
 =?utf-8?B?NE1HOGJ3T21nQ0FRU3ZlQkJtTk9jVHdsTVpPMzVueTRadmlqRG5YbEZ2RHQx?=
 =?utf-8?B?alJoNUZkcENITTRRRGd0TmxqdXViNVZ0N1BxRHBsSURqRFBuNmJMblgvbTdw?=
 =?utf-8?B?akdqK3prUlFEQzlOTVhFaVJmZTF2WVdUcUdhZi9QSzhqVUtySnB3MU9sVVJS?=
 =?utf-8?B?Skx2SzJlcWdPQ2JUUFdwNEpXeVZpSVJ5Rkt3SU5sak5ycXovdTVna21ZUTRV?=
 =?utf-8?B?QlJ4ekUzeHR2WHFvdDVxNGd1WCtZdnpPZmtZZkpJWGF1K2tQa1lBQ0hEL2dY?=
 =?utf-8?B?TzBzZzUxZ2NkUlRaSnBUMkVaS1hnNlB5S3VPb0JXZENpS1F6NmFKb2ZFU2wz?=
 =?utf-8?B?QW92bEQ0cGRublNqWVRMNDZYcGM2bTVjbWxzVUpnR0tSZXNxV1E4bE02anJB?=
 =?utf-8?B?VWV2RGtBL0ZGNWdrQ01pOVVLZXhyNG9NZWNudndZNjFzampoV1RVTk14RFhL?=
 =?utf-8?B?eTVzZnpMUHJvWlh6dit6OUlYUFNGWm9BaHlLQUo3cjZlMlNUM1BNYUpiNVpx?=
 =?utf-8?B?RjhXMDJpTldONTFuSlhqbEIxc0dRTG5QOTFCTVR1OUczenVzUmxHZE5TQ0Nu?=
 =?utf-8?B?ek5mdi9HSVRhSVM0VHc5YnQ3akVqdWJxWUxadzJBQjlUZWlnTHhzRUFhc1pp?=
 =?utf-8?B?cEVxb2t3Zno0NWNrdVRlNzgrRGUvcVpidXowbER2L0x1ajhTWmVOeVdBRzdq?=
 =?utf-8?B?Z1dZT0FTWlowKzY1VzEwWlRobFdnTWloYTdCVldXYm10bndNYzdublN3d0Zo?=
 =?utf-8?B?MkJ6ZlJNRUhVR2pVTnlSakN3amh0dkhLTlZra2Rxc2d1Y1gwS0JvekVMYlh3?=
 =?utf-8?B?a3ROSGdCZXU0ZktseW41V05ua1dpSEVBNTRtVW85Tk9CZmRDdWhENXBVbGhH?=
 =?utf-8?B?d1A2ajZIanU2YWNGM3R1cW1IeGwzLzV5c2ZzOVR2NFA3aGk1WGVReXRZT2V6?=
 =?utf-8?B?d2N4YUxEWW5sYklLVUJ4SlRTVlg2MXY4bjNxdnJUeVZOZnRBenZjNzdIUDRK?=
 =?utf-8?B?ZUFlOHpQamhWYUVvMzNSb0NJUisxK2JocFNLejZGNnNKMXJYS29hTHgySkt0?=
 =?utf-8?B?MmFyQ0Z2ZGlSN3piS3JXYTdPUk5jQ0pCV2QreTg4N1ozL1ZuL2JWQ0d4K3R5?=
 =?utf-8?B?TVgwTmFXNGltRXdGTnVRdHZPdkJJakREbVh4TG51ZnVKUjdocWpvL1JlcVFE?=
 =?utf-8?B?WWxjaVhPV0VOcnJNazZmN01LY0dPVmV4Y2VwSnViTXZPbWsyTlU1WHg4VjZ4?=
 =?utf-8?B?cXpNMUVjYWxPYkNHUjUzUGE0b1RLaklBVS9Gb2dycmdwRjh2cFlsU3lzbTdX?=
 =?utf-8?B?M2Y2SUI5MDJjWG0vNXZkWUp1UFUydTgwMWdyRmtsOWI4ZGpEVXVGQ3NkQ1FX?=
 =?utf-8?B?SHVzeXhzbXVDYStRd2VTV0xBcFdlV3g3anVnaUg1dHVwQlhURW1yRVhHNnpr?=
 =?utf-8?B?YUE0QUdIODd3YUFFS0ZLNzJXWG5HN2FEVzVubUFsVlUrQlFrUkU3Z2VjdU9G?=
 =?utf-8?B?azhpbi9lTE5rdzFuSXFRWnF3b3V6T1lMZzl2TU9uRTFkeVFBaWc2eEU2bm5u?=
 =?utf-8?B?ZCtjaVBuTHp6eDNaaXFVN1NUa255eFpwZjBWMG15LzlMNnh1ZElkK3lqV2tn?=
 =?utf-8?B?UHNRMjFVYmNxZGhYQy83VWtyUzd5SDJQZGlIVXFVcThsc2MwaWtIbWFMRGZk?=
 =?utf-8?B?Y1JLSm9xYyt3TUxjNGdPM1pUOUJ0ZGhQOHFGTVluUDV4eWdNc2xabkRMVGhz?=
 =?utf-8?B?QnVtQ1RRM291L3I0cTllK3h6TmxJUXFyaDlYamM5KzR5QXdiRFhYaGNMRFlQ?=
 =?utf-8?Q?YZYiuj0sMa6ylACr2iXDjoZxK?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 8465c673-5a75-43ce-9f7b-08dc482eae38
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2024 16:07:30.9328
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: QfiJWMtI13vPRDWkicPnaX7X0/Ezge53fKv9ncmr/05+9ADw3TsHe6Y4oSzbcb4njjcCofYEaPUNkcE7nUOMLQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7772

From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
INTx IRQs by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. So, this implementation supports the data-less messages only
for now.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
 drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index df2575ec5f44c..ba909fade9db1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
 			      upper_32_bits(atu->pci_addr));
 
-	val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
+	val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
 	if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
 	    dw_pcie_ver_is_ge(pci, 460A))
 		val |= PCIE_ATU_INCREASE_REGION_SIZE;
@@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
 
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+	val = PCIE_ATU_ENABLE;
+	if (atu->type == PCIE_ATU_TYPE_MSG) {
+		/* The data-less messages only for now */
+		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+	}
+	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
 
 	/*
 	 * Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d21db82e586d5..703b50bc5e0f1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -148,11 +148,13 @@
 #define PCIE_ATU_TYPE_IO		0x2
 #define PCIE_ATU_TYPE_CFG0		0x4
 #define PCIE_ATU_TYPE_CFG1		0x5
+#define PCIE_ATU_TYPE_MSG		0x10
 #define PCIE_ATU_TD			BIT(8)
 #define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
 #define PCIE_ATU_REGION_CTRL2		0x004
 #define PCIE_ATU_ENABLE			BIT(31)
 #define PCIE_ATU_BAR_MODE_ENABLE	BIT(30)
+#define PCIE_ATU_INHIBIT_PAYLOAD	BIT(22)
 #define PCIE_ATU_FUNC_NUM_MATCH_EN      BIT(19)
 #define PCIE_ATU_LOWER_BASE		0x008
 #define PCIE_ATU_UPPER_BASE		0x00C
@@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg {
 	int index;
 	int type;
 	u8 func_no;
+	u8 code;
+	u8 routing;
 	u64 cpu_addr;
 	u64 pci_addr;
 	u64 size;

-- 
2.34.1