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Message-ID: <e589e7d5-c83a-4b33-8504-e3174cc4e534@intel.com>
Date: Tue, 19 Mar 2024 11:31:38 -0700
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Subject: Re: [PATCH v2 1/1] cxl/mem: Fix for the index of Clear Event Record
 Handle
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To: Dan Williams <dan.j.williams@intel.com>,
 Jonathan Cameron <Jonathan.Cameron@huawei.com>,
 Yuquan Wang <wangyuquan1236@phytium.com.cn>
Cc: ira.weiny@intel.com, linux-cxl@vger.kernel.org,
 linux-kernel@vger.kernel.org, qemu-devel@nongnu.org, chenbaozi@phytium.com.cn
References: <20240318022928.509130-1-wangyuquan1236@phytium.com.cn>
 <20240318022928.509130-2-wangyuquan1236@phytium.com.cn>
 <20240318105748.000072c5@Huawei.com>
 <65f8de878e8e1_7702a294f4@dwillia2-xfh.jf.intel.com.notmuch>
From: Dave Jiang <dave.jiang@intel.com>
In-Reply-To: <65f8de878e8e1_7702a294f4@dwillia2-xfh.jf.intel.com.notmuch>
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On 3/18/24 5:38 PM, Dan Williams wrote:
> Jonathan Cameron wrote:
>> On Mon, 18 Mar 2024 10:29:28 +0800
>> Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote:
>>
>>> The dev_dbg info for Clear Event Records mailbox command would report
>>> the handle of the next record to clear not the current one.
>>>
>>> This was because the index 'i' had incremented before printing the
>>> current handle value.
>>>
>>> Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
>>> ---
>>>  drivers/cxl/core/mbox.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
>>> index 9adda4795eb7..b810a6aa3010 100644
>>> --- a/drivers/cxl/core/mbox.c
>>> +++ b/drivers/cxl/core/mbox.c
>>> @@ -915,7 +915,7 @@ static int cxl_clear_event_record(struct cxl_memdev_state *mds,
>>>  
>>>  		payload->handles[i++] = gen->hdr.handle;
>>>  		dev_dbg(mds->cxlds.dev, "Event log '%d': Clearing %u\n", log,
>>> -			le16_to_cpu(payload->handles[i]));
>>> +			le16_to_cpu(payload->handles[i-1]));
>> Trivial but needs spaces around the -. e.g.  [i - 1] 
>>
>> Maybe Dan can fix up whilst applying.
>>
>> Otherwise
>>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> I have enlisted Dave to start wrangling CXL kernel patches upstream, and
> I will fall back to just reviewing.
> 
> Dave, you can add my:
> 
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> 
> ...with the same caveat as above.

Applied, updated, and added 
Fixes: 6ebe28f9ec72 ("cxl/mem: Read, trace, and clear events on driver load")

>