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Date: Wed, 20 Mar 2024 08:23:41 +0100
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Subject: Re: [PATCH v4 1/3] clk: samsung: Implement manual PLL control for
 ARM64 SoCs
To: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>,
 Chanwoo Choi <cw00.choi@samsung.com>, Alim Akhtar <alim.akhtar@samsung.com>,
 Michael Turquette <mturquette@baylibre.com>, Stephen Boyd
 <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>, Tomasz Figa <tomasz.figa@gmail.com>,
 linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
 devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-kernel@vger.kernel.org
References: <20240301015118.30072-1-semen.protsenko@linaro.org>
 <CAPLW+4=_yD3ShU5DvLWFyEzVrVHNVCsB+4bVkP+x_boRmC-vEw@mail.gmail.com>
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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On 19/03/2024 19:47, Sam Protsenko wrote:
> On Thu, Feb 29, 2024 at 7:51 PM Sam Protsenko
> <semen.protsenko@linaro.org> wrote:
>>
>> Some ARM64 Exynos chips are capable to control PLL clocks automatically.
>> For those chips, whether the PLL is controlled automatically or manually
>> is chosen in PLL_CON1 register with next bits:
>>
>>     [28]  ENABLE_AUTOMATIC_CLKGATING
>>     [1]   MANUAL_PLL_CTRL
>>     [0]   AUTO_PLL_CTRL
>>
>> The bl2 bootloader sets 0x10000001 value for some PLL_CON1 registers,
>> which means any attempt to control those PLLs manually (e.g.
>> disabling/enabling those PLLs or changing MUX parent clocks) would lead
>> to PLL lock timeout with error message like this:
>>
>>     Could not lock PLL ...
>>
>> At the moment, all Samsung clock drivers implement manual clock control.
>> So in order to make it possible to control PLLs, corresponding PLL_CON1
>> registers should be set to 0x2 first.
>>
>> Some older ARM64 chips don't implement the automatic clock control
>> though. It also might be desirable to configure some PLLs for manual
>> control, while keeping the default configuration for the rest. So it'd
>> convenient to choose this PLL mode for each CMU separately. Introduce
>> .manual_plls field to CMU structure to choose the PLL control mode.
>> Because it'll be initialized with "false" in all existing CMU
>> structures by default, it won't affect any existing clock drivers,
>> allowing for this feature to be enabled gradually when it's needed with
>> no change for the rest of users. In case .manual_plls is set, set
>> PLL_CON1 registers to manual control, akin to what's already done for
>> gate clocks in exynos_arm64_init_clocks(). Of course, PLL_CON1 registers
>> should be added to corresponding struct samsung_cmu_info::clk_regs array
>> to make sure they get initialized.
>>
>> No functional change. This patch adds a feature, but doesn't enable it
>> for any users.
>>
>> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
>> ---
> 
> Hi Krzysztof,
> 
> If it looks ok to you, can you please apply this series?
> 
>     [PATCH 1/3] clk: samsung: Implement manual PLL control for ARM64 SoCs
>     [PATCH 2/3] clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
>     [PATCH 3/3] arm64: dts: exynos: Add CPU clocks for Exynos850
> 
> That concludes my efforts on CPU clock enablement in Exynos850.

Please do not ping during merge window, for anything else than fixes
(and me only for fixes being serious regressions or serious issues, not
for fixing something which never worked thus will not get to fixes
branch). Not only me, but don't ping that way any of the maintainers.

Best regards,
Krzysztof