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b=SW6BUJlsDX/vH6gjWlpT+cbGApubryaDyEF8qDyDRffiR8F8JyIwyHOJ+GRsIFzBo uDfOMHVc+690RVFFaVnT6KvRq57AOMDFG8hGl66yVb4i18Af+br29PzGSi8oUQXTc8 sLEEsQ/2rahhL4NQYDVDANRz/3xsfoNC8uxbwzWc= Received: from [127.0.0.1] (unknown [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 1B11B6776E; Wed, 20 Mar 2024 08:52:14 -0400 (EDT) Message-ID: <2d3d529e006a6fbef6fe4a8a20b3eb23fa476ff7.camel@xry111.site> Subject: Re: [PATCH v8 4/4] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD From: Xi Ruoyao To: Maxim Kiselev Cc: Albert Ou , Conor Dooley , devicetree@vger.kernel.org, dfustini@baylibre.com, guoren@kernel.org, jkridner@beagleboard.org, jszhang@kernel.org, Krzysztof Kozlowski , open list , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , robertcnelson@beagleboard.org, Rob Herring , wefu@redhat.com Date: Wed, 20 Mar 2024 20:52:13 +0800 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2024-03-20 at 15:28 +0300, Maxim Kiselev wrote: > Hi Xi, Drew >=20 > I have the same problem with SD on my LicheePi 4A. >=20 > After some investigations I found how to fix this tuning error. > Here is the patch that increases tuning loop count from > 40(MAX_TUNING_LOOP at sdhci.c) to 128. >=20 > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c > b/drivers/mmc/host/sdhci-of-dwcmshc.c > index 8d6cfb648096..da8f5820fb69 100644 > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c > @@ -706,6 +706,7 @@ static int th1520_execute_tuning(struct sdhci_host > *host, u32 opcode) >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* perform tuning */ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sdhci_start_tuning(host); > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 host->tuning_loop_count =3D 128: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 host->tuning_err =3D __sdhci_e= xecute_tuning(host, opcode); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (host->tuning_err) { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 /* disable auto-tuning upon tuning error */ >=20 > After that change tuning works fine. The same value of loop count is > used in RevyOS BSP > https://github.com/revyos/thead-kernel/blob/c6d4e5df18a17903d012ffd89e67d= 0ee5ce6cf2d/drivers/mmc/host/sdhci-of-dwcmshc.c#L185 >=20 > Honestly, it looks a little bit strange for me. >=20 > It seems that the tuning algorithm requires to move through > all the taps of delay line(128 taps?) even if we use THRESHOLD_MODE > instend LARGEST_WIN_MODE (I mean bit 2 in AT_CTRL_R(0x540) register). >=20 > Xi, could you also test my fix on your board? I'll try it this weekend. Now having some work with "real time priority" to do :(. --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University