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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR18MB4206.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf55713f-b561-44d8-4434-08dc48faff7e X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Mar 2024 16:30:04.4708 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gZn6UJFqvFtOxJw8kG+Yg1AMII9/7X2fXc+3/3DsVIY9OLko3UTiuLWUkLLhWit8N5KpVF3so9ImcXyJw40Vvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO3PR18MB4942 X-Proofpoint-ORIG-GUID: TCmWnrIxTquTDgedVejfm4UAZjhtKLoa X-Proofpoint-GUID: TCmWnrIxTquTDgedVejfm4UAZjhtKLoa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-20_10,2024-03-18_03,2023-05-22_02 Hi Andi, We have updated these patches as per the comments. Can you please review them. Thanks, Piyush > -----Original Message----- > From: Piyush Malgujar > Sent: Friday, February 23, 2024 6:27 PM > To: linux-i2c@vger.kernel.org; linux-kernel@vger.kernel.org; > andi.shyti@kernel.org > Cc: Suneel Garapati ; Chandrakala Chavva > ; Jayanthi Annadurai ; > Piyush Malgujar > Subject: [PATCH v4 1/4] i2c: thunderx: Clock divisor logic changes >=20 > From: Suneel Garapati >=20 > Handle changes to clock divisor logic for OcteonTX2 SoC family using > subsystem ID and using default reference clock source as 100MHz. >=20 > Signed-off-by: Suneel Garapati > Signed-off-by: Piyush Malgujar > Acked-by: Andi Shyti > --- > drivers/i2c/busses/i2c-octeon-core.c | 38 +++++++++++++++++++++--- > drivers/i2c/busses/i2c-octeon-core.h | 15 ++++++++++ > drivers/i2c/busses/i2c-thunderx-pcidrv.c | 7 +++++ > 3 files changed, 56 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2= c- > octeon-core.c > index > 845eda70b8cab52a0453c9f4cb545010fba4305d..10330ed3203f9fd99d5c04db > af29a9bd49ad0f4a 100644 > --- a/drivers/i2c/busses/i2c-octeon-core.c > +++ b/drivers/i2c/busses/i2c-octeon-core.c > @@ -17,9 +17,14 @@ > #include > #include > #include > +#include >=20 > #include "i2c-octeon-core.h" >=20 > +#define INITIAL_DELTA_HZ 1000000 > +#define TWSI_MASTER_CLK_REG_DEF_VAL 0x18 > +#define TWSI_MASTER_CLK_REG_OTX2_VAL 0x3 > + > /* interrupt service routine */ > irqreturn_t octeon_i2c_isr(int irq, void *dev_id) { @@ -658,31 +663,56 = @@ > int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int n= um) > void octeon_i2c_set_clock(struct octeon_i2c *i2c) { > int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; > - int thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz =3D 1000000; > + unsigned int mdiv_min =3D 2; > + /* > + * Find divisors to produce target frequency, start with large delta > + * to cover wider range of divisors, note thp =3D TCLK half period. > + */ > + unsigned int thp =3D TWSI_MASTER_CLK_REG_DEF_VAL, mdiv =3D 2, ndiv =3D > 0; > + unsigned int delta_hz =3D INITIAL_DELTA_HZ; > + > + bool is_plat_otx2 =3D octeon_i2c_is_otx2(to_pci_dev(i2c->dev)); > + > + if (is_plat_otx2) { > + thp =3D TWSI_MASTER_CLK_REG_OTX2_VAL; > + mdiv_min =3D 0; > + } >=20 > for (ndiv_idx =3D 0; ndiv_idx < 8 && delta_hz !=3D 0; ndiv_idx++) { > /* > * An mdiv value of less than 2 seems to not work well > * with ds1337 RTCs, so we constrain it to larger values. > */ > - for (mdiv_idx =3D 15; mdiv_idx >=3D 2 && delta_hz !=3D 0; mdiv_idx- > -) { > + for (mdiv_idx =3D 15; mdiv_idx >=3D mdiv_min && delta_hz !=3D 0; > +mdiv_idx--) { > /* > * For given ndiv and mdiv values check the > * two closest thp values. > */ > tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * 10; > tclk *=3D (1 << ndiv_idx); > - thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; > + if (is_plat_otx2) > + thp_base =3D (i2c->sys_freq / tclk) - 2; > + else > + thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; >=20 > for (inc =3D 0; inc <=3D 1; inc++) { > thp_idx =3D thp_base + inc; > if (thp_idx < 5 || thp_idx > 0xff) > continue; >=20 > - foscl =3D i2c->sys_freq / (2 * (thp_idx + 1)); > + if (is_plat_otx2) > + foscl =3D i2c->sys_freq / (thp_idx + 2); > + else > + foscl =3D i2c->sys_freq / > + (2 * (thp_idx + 1)); > foscl =3D foscl / (1 << ndiv_idx); > foscl =3D foscl / (mdiv_idx + 1) / 10; > diff =3D abs(foscl - i2c->twsi_freq); > + /* > + * Diff holds difference between calculated > frequency > + * value vs desired frequency. > + * Delta_hz is updated with last minimum diff. > + */ > if (diff < delta_hz) { > delta_hz =3D diff; > thp =3D thp_idx; > diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2= c- > octeon-core.h > index > 9bb9f64fdda0392364638ecbaafe3fab5612baf6..8a0033c94a8a291fb255b0da0 > 3858274035c46f4 100644 > --- a/drivers/i2c/busses/i2c-octeon-core.h > +++ b/drivers/i2c/busses/i2c-octeon-core.h > @@ -7,6 +7,7 @@ > #include > #include > #include > +#include >=20 > /* Controller command patterns */ > #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ > @@ -211,6 +212,20 @@ static inline void octeon_i2c_write_int(struct > octeon_i2c *i2c, u64 data) > octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } >=20 > +#define PCI_SUBSYS_DEVID_9XXX 0xB > +/** > + * octeon_i2c_is_otx2 - check for chip ID > + * @pdev: PCI dev structure > + * > + * Returns TRUE if OcteonTX2, FALSE otherwise. > + */ > +static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) { > + u32 chip_id =3D (pdev->subsystem_device >> 12) & 0xF; > + > + return (chip_id =3D=3D PCI_SUBSYS_DEVID_9XXX); } > + > /* Prototypes */ > irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(= struct > i2c_adapter *adap, struct i2c_msg *msgs, int num); diff --git > a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thund= erx- > pcidrv.c > index > a77cd86fe75ed7401bc041b27c651b9fedf67285..75569774003857dc984e8540 > ef8f4d1bb084cfb0 100644 > --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c > +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c > @@ -28,6 +28,7 @@ > #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012 >=20 > #define SYS_FREQ_DEFAULT 700000000 > +#define OTX2_REF_FREQ_DEFAULT 100000000 >=20 > #define TWSI_INT_ENA_W1C 0x1028 > #define TWSI_INT_ENA_W1S 0x1030 > @@ -205,6 +206,12 @@ static int thunder_i2c_probe_pci(struct pci_dev > *pdev, > if (ret) > goto error; >=20 > + /* > + * For OcteonTX2 chips, set reference frequency to 100MHz > + * as refclk_src in TWSI_MODE register defaults to 100MHz. > + */ > + if (octeon_i2c_is_otx2(pdev)) > + i2c->sys_freq =3D OTX2_REF_FREQ_DEFAULT; > octeon_i2c_set_clock(i2c); >=20 > i2c->adap =3D thunderx_i2c_ops; > -- > 2.43.0