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Thu, 21 Mar 2024 04:32:43 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 20 Mar 2024 21:32:38 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH 2/2] clk: qcom: add IPQ9574 interconnect clocks support Date: Thu, 21 Mar 2024 10:01:49 +0530 Message-ID: <20240321043149.2739204-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240321043149.2739204-1-quic_varada@quicinc.com> References: <20240321043149.2739204-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 42bWRczlBXmHoXRCekydr70oaTlrGL2J X-Proofpoint-GUID: 42bWRczlBXmHoXRCekydr70oaTlrGL2J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_01,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403210028 Unlike MSM platforms that manage NoC related clocks and scaling from RPM, IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for accessing the peripheral controllers present on these NoCs. Hence adding a minimalistic interconnect driver that can enable the relevant clocks. This is similar to msm8996-cbf's usage of icc-clk framework. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 + drivers/clk/qcom/gcc-ipq9574.c | 75 ++++++++++++++++++++++++++- 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..efffbd085715 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -306,6 +307,7 @@ gcc: clock-controller@1800000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + #interconnect-cells = <1>; }; tcsr_mutex: hwlock@1905000 { diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0a3f846695b8..edbf223719e4 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -9,9 +9,16 @@ #include #include #include +#if IS_ENABLED(CONFIG_INTERCONNECT) +#include +#include +#endif #include #include +#if IS_ENABLED(CONFIG_INTERCONNECT) +#include +#endif #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -4301,6 +4308,35 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, }; + +#if IS_ENABLED(CONFIG_INTERCONNECT) +static struct icc_clk_data *icc_ipq9574; + +static int noc_clks[] = { + GCC_ANOC_PCIE0_1LANE_M_CLK, + GCC_SNOC_PCIE0_1LANE_S_CLK, + GCC_ANOC_PCIE1_1LANE_M_CLK, + GCC_SNOC_PCIE1_1LANE_S_CLK, + GCC_ANOC_PCIE2_2LANE_M_CLK, + GCC_SNOC_PCIE2_2LANE_S_CLK, + GCC_ANOC_PCIE3_2LANE_M_CLK, + GCC_SNOC_PCIE3_2LANE_S_CLK, + GCC_SNOC_USB_CLK, + GCC_ANOC_USB_AXI_CLK, + GCC_NSSNOC_NSSCC_CLK, + GCC_NSSNOC_SNOC_CLK, + GCC_NSSNOC_SNOC_1_CLK, + GCC_NSSNOC_PCNOC_1_CLK, + GCC_NSSNOC_QOSGEN_REF_CLK, + GCC_NSSNOC_TIMEOUT_REF_CLK, + GCC_NSSNOC_XO_DCD_CLK, + GCC_NSSNOC_ATB_CLK, + GCC_MEM_NOC_NSSNOC_CLK, + GCC_NSSNOC_MEMNOC_CLK, + GCC_NSSNOC_MEM_NOC_1_CLK, +}; +#endif + static const struct of_device_id gcc_ipq9574_match_table[] = { { .compatible = "qcom,ipq9574-gcc" }, { } @@ -4327,7 +4363,44 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = { static int gcc_ipq9574_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq9574_desc); + int ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc); +#if IS_ENABLED(CONFIG_INTERCONNECT) + struct icc_provider *provider; + struct icc_clk_data *icd; + int i; +#endif + + if (ret) + return dev_err_probe(&pdev->dev, ret, "%s failed\n", __func__); + +#if IS_ENABLED(CONFIG_INTERCONNECT) + icd = devm_kmalloc(&pdev->dev, ARRAY_SIZE(noc_clks) * sizeof(*icd), + GFP_KERNEL); + + if (IS_ERR_OR_NULL(icd)) + return dev_err_probe(&pdev->dev, PTR_ERR(icd), + "%s malloc failed\n", __func__); + + icc_ipq9574 = icd; + + for (i = 0; i < ARRAY_SIZE(noc_clks); i++, icd++) { + icd->clk = gcc_ipq9574_clks[noc_clks[i]]->hw.clk; + if (IS_ERR_OR_NULL(icd->clk)) { + dev_err(&pdev->dev, "%s: %d clock not found\n", + __func__, noc_clks[i]); + return -ENOENT; + } + icd->name = clk_hw_get_name(&gcc_ipq9574_clks[noc_clks[i]]->hw); + } + + provider = icc_clk_register(&pdev->dev, IPQ_APPS_ID, + ARRAY_SIZE(noc_clks), icc_ipq9574); + if (IS_ERR_OR_NULL(provider)) + return dev_err_probe(&pdev->dev, PTR_ERR(provider), + "%s: icc_clk_register failed\n", __func__); +#endif + + return 0; } static struct platform_driver gcc_ipq9574_driver = { -- 2.34.1