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[139.178.88.99]) by mx.google.com with ESMTPS id x42-20020a056a0018aa00b006e8f8db2051si30905pfh.353.2024.03.21.09.30.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 09:30:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-110340-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=FbmFLEAR; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-110340-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-110340-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 3AE39283658 for ; Thu, 21 Mar 2024 16:30:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 46E5212CDBF; Thu, 21 Mar 2024 16:29:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FbmFLEAR" Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55A8F12C532; Thu, 21 Mar 2024 16:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711038580; cv=none; b=UuN0bXXz+JuFmM/Yox6NAGXY5P/9sFJF0wWGxnstXPlP2wnzDE6G8cv8CjRjePaMcQKqr6vJxekVPh4jsxR6fOZUsKZaecos8qDoEM7byiltMUVpIi15Wij9q5s46WXc9eps8rN2x8FCUNY9UQO+BQk1YAQGbmgY91LT9uNxde0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711038580; c=relaxed/simple; bh=Dm1PpESmKUiBkJ+3cICRSDiBnf/1JiIG6XDigLGXMlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AROueQ8VfxrhV3v12Odb4QcyWZrV8IJToXoM4Da0QE+ttk9MWoIGRAmhU2WpMxgd6Rq+7BaDBtD0ixZtc/PN4cImlvBuy3PVwziHEHbCNDZFKrkeEHg4og7SFRh4QshXBP8+7BbbytDjgbrrfCin5y1Ru9UiX4FV69RrS9K4wzA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FbmFLEAR; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPS id F12EBC433C7; Thu, 21 Mar 2024 16:29:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711038580; bh=Dm1PpESmKUiBkJ+3cICRSDiBnf/1JiIG6XDigLGXMlQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FbmFLEAR2OjkUz89fFAGbWQaIBm7VPp+wrODGf3cgpaW90dcMMuLPUIBy4ru/hhLb zfgNOMoZT4E2PAniw6E7a3cgj69iN8oHRRILIap1aZb7vlU72m1BtedZcv0Ia+qf9T vuAP8YSIFtNAijVsMjR9CQ8nG8mT4zlWwoYDf19CkpQDwdS7pbWPG585rZI/KUoNIm AVyj7tERnH4WO6w+4cFron94YQimE9rxVXrTVVp+Ge8/M9SV6CstakFSIFlInqNC+k YN6FSt43taTpm3dvkiUPLu4r8exbptcplSQC7tDyKaEKHjZXtxMq7aDLz35zQTva21 c6h466+5AOmww== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAD1ECD11C2; Thu, 21 Mar 2024 16:29:39 +0000 (UTC) From: =?utf-8?q?Ar=C4=B1n=C3=A7_=C3=9CNAL_via_B4_Relay?= Date: Thu, 21 Mar 2024 19:29:13 +0300 Subject: [PATCH net v2 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on all boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20240321-for-net-mt7530-fix-eee-for-mt7531-mt7988-v2-1-9af9d5041bfe@arinc9.com> References: <20240321-for-net-mt7530-fix-eee-for-mt7531-mt7988-v2-0-9af9d5041bfe@arinc9.com> In-Reply-To: <20240321-for-net-mt7530-fix-eee-for-mt7531-mt7988-v2-0-9af9d5041bfe@arinc9.com> To: Daniel Golle , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Russell King , SkyLake Huang , Heiner Kallweit Cc: Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, =?utf-8?q?Ar=C4=B1n=C3=A7_=C3=9CNAL?= , Florian Fainelli X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711038558; l=3102; i=arinc.unal@arinc9.com; s=arinc9-patatt; h=from:subject:message-id; bh=jPUSZ3Gz1HwFE6kGrRuGpoudPKmyUngv0UO3D4WqCPk=; b=PDdYcDWLl5PpsAn992chSxQxfWJGD18RI8e2IpPDL4UEksOruuIlksuJkAwm3bSzIZepdQ05O Pv6HZ7ZaNQkBAN7PxMeFnwusBGvksLdTarcCSmntqk+/6dnQ1ijKJO6 X-Developer-Key: i=arinc.unal@arinc9.com; a=ed25519; pk=VmvgMWwm73yVIrlyJYvGtnXkQJy9CvbaeEqPQO9Z4kA= X-Endpoint-Received: by B4 Relay for arinc.unal@arinc9.com/arinc9-patatt with auth_id=115 X-Original-From: =?utf-8?q?Ar=C4=B1n=C3=A7_=C3=9CNAL?= Reply-To: arinc.unal@arinc9.com From: Arınç ÜNAL The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is enabled on MT7531 switch MACs either by pulling the LAN2LED0 pin low on the board (bootstrapping), or unsetting the EEE_DIS bit on the trap register. There are existing boards that were not designed to pull the pin low. Therefore, unset the EEE_DIS bit on the trap register. Unlike MT7530, the modifiable trap register won't be populated identical to the trap status register after reset. Therefore, read from the trap status register, modify the bits, then write to the modifiable trap register. My testing on MT7531 shows a certain amount of traffic loss when EEE is enabled. That said, I haven't come across a board that enables EEE. So enable EEE on the switch MACs but disable EEE advertisement on the switch PHYs. This way, we don't change the behaviour of the majority of the boards that have this switch. With this change, EEE can now be enabled using ethtool. The disable EEE bit on the trap pertains to the LAN2LED0 pin which is usually used to control an LED. Once the bit is unset, the pin will be low. That will make the active low LED turn on. The pin is controlled by the switch PHY. It seems that the PHY controls the pin in the way that it inverts the pin state. That means depending on the wiring of the LED connected to LAN2LED0 on the board, the LED may be on without an active link. Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") Reviewed-by: Florian Fainelli Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 14 ++++++++++++++ drivers/net/dsa/mt7530.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 678b51f9cea6..6aa99b590329 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2458,6 +2458,20 @@ mt7531_setup(struct dsa_switch *ds) /* Reset the switch through internal reset */ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); + /* Allow modifying the trap and enable Energy-Efficient Ethernet (EEE). + */ + val = mt7530_read(priv, MT7531_HWTRAP); + val |= CHG_STRAP; + val &= ~EEE_DIS; + mt7530_write(priv, MT7530_MHWTRAP, val); + + /* Disable EEE advertisement on the switch PHYs. */ + for (i = MT753X_CTRL_PHY_ADDR; + i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) { + mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, + 0); + } + if (!priv->p5_sgmii) { mt7531_pll_setup(priv); } else { diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index a71166e0a7fc..509ed5362236 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -457,6 +457,7 @@ enum mt7531_clk_skew { #define XTAL_FSEL_M BIT(7) #define PHY_EN BIT(6) #define CHG_STRAP BIT(8) +#define EEE_DIS BIT(4) /* Register for hw trap modification */ #define MT7530_MHWTRAP 0x7804 -- 2.40.1