Received-SPF: pass (google.com: domain of linux-kernel+bounces-111028-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Precedence: bulk
MIME-Version: 1.0
References: <20240321195309.484275-1-ubizjak@gmail.com> <feb68b86-899e-42a2-a680-4a73366e540d@redhat.com>
In-Reply-To: <feb68b86-899e-42a2-a680-4a73366e540d@redhat.com>
From: Uros Bizjak <ubizjak@gmail.com>
Date: Fri, 22 Mar 2024 07:51:45 +0100
Message-ID: <CAFULd4aR_zmUneh=3RKHnbT=8Fc_kCkLHs54aUVjfXoAJdXdGQ@mail.gmail.com>
Subject: Re: [PATCH] locking/qspinlock: Use atomic_try_cmpxchg_relaxed() in xchg_tail()
To: Waiman Long <longman@redhat.com>
Cc: linux-kernel@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>, 
	Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>, Boqun Feng <boqun.feng@gmail.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Fri, Mar 22, 2024 at 12:52=E2=80=AFAM Waiman Long <longman@redhat.com> w=
rote:
>
> On 3/21/24 15:52, Uros Bizjak wrote:
> > Use atomic_try_cmpxchg_relaxed(*ptr, &old, new) instead of
> > atomic_cmpxchg_relaxed (*ptr, old, new) =3D=3D old in xchg_tail().
> > x86 CMPXCHG instruction returns success in ZF flag,
> > so this change saves a compare after cmpxchg.
> >
> > No functional change intended.
> >
> > Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
> > Cc: Peter Zijlstra <peterz@infradead.org>
> > Cc: Ingo Molnar <mingo@redhat.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Waiman Long <longman@redhat.com>
> > Cc: Boqun Feng <boqun.feng@gmail.com>
> > ---
> >   kernel/locking/qspinlock.c | 13 +++++--------
> >   1 file changed, 5 insertions(+), 8 deletions(-)
> >
> > diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
> > index ebe6b8ec7cb3..1df5fef8a656 100644
> > --- a/kernel/locking/qspinlock.c
> > +++ b/kernel/locking/qspinlock.c
> > @@ -220,21 +220,18 @@ static __always_inline void clear_pending_set_loc=
ked(struct qspinlock *lock)
> >    */
> >   static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail=
)
> >   {
> > -     u32 old, new, val =3D atomic_read(&lock->val);
> > +     u32 old, new;
> >
> > -     for (;;) {
> > -             new =3D (val & _Q_LOCKED_PENDING_MASK) | tail;
> > +     old =3D atomic_read(&lock->val);
> > +     do {
> > +             new =3D (old & _Q_LOCKED_PENDING_MASK) | tail;
> >               /*
> >                * We can use relaxed semantics since the caller ensures =
that
> >                * the MCS node is properly initialized before updating t=
he
> >                * tail.
> >                */
> > -             old =3D atomic_cmpxchg_relaxed(&lock->val, val, new);
> > -             if (old =3D=3D val)
> > -                     break;
> > +     } while (!atomic_try_cmpxchg_relaxed(&lock->val, &old, new));
> >
> > -             val =3D old;
> > -     }
> >       return old;
> >   }
> >   #endif /* _Q_PENDING_BITS =3D=3D 8 */
>
> LGTM, note that this xchg_tail() variant is not used in all the distros
> that I am aware of as it requires NR_CPUS >=3D 16k.

Yes, I am aware of this. I have tested the patch simply by
unconditionally setting _Q_PENDING_BITS to 1 in
include/asm-generic/qspinlock_types.h.
>
> Reviewed-by: Waiman Long <longman@redhat.com>

Thanks,
Uros.