Received: by 2002:ab2:6857:0:b0:1ef:ffd0:ce49 with SMTP id l23csp1086182lqp; Fri, 22 Mar 2024 05:25:50 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCWSEDA5vdJh4RGlAtpgfZgnMPaM9S94Yj3AjjSKVYGc452DEXxSbTjBFZpxGEaPaLK1X8ya8+fFVVl5kIqKhtGtVYrD6SG1zoDPgPGn8g== X-Google-Smtp-Source: AGHT+IHmS4eCyAy3LeEj0xTniJgqQ+TqWGpwWVKErefR4uSFf/IRVvyH3NaexIFACjwGP7ir74Td X-Received: by 2002:a17:906:7fd0:b0:a47:300b:187b with SMTP id r16-20020a1709067fd000b00a47300b187bmr1136279ejs.34.1711110349888; Fri, 22 Mar 2024 05:25:49 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1711110349; cv=pass; d=google.com; s=arc-20160816; b=Q3kji7vXkHwVPvm/HTdOqXTbgz9oBZysrubjZmFbw70NIp4Dv+kziU/11hj/aNrSep BO7z9GwrJ7VwJwiVx/jYXv8QGhcMF5Xrt9i9bswSPu7oG1vFyeXAWtPUuWanizJyYJDn 6YhU1WwO4zhoIJvsCgJkF2It5DiSYQyQ+ahSxs+64+FozYK/6OWKxV/CTWVhenpj7D38 A0OuX/oHlfowBl0gOV/gBhP+FndAzIjogSaiWuk5dn8ewc5HMmo8NytLkwTg2jyiL5Ui JqY1PJqwTj+6Gssfzjca2Zwy0aue4vpcUL0hr3rbt7AQ56ftTomplCorqcwRnW9otv+D lqNQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :references:message-id:subject:cc:to:from:date; bh=Up3fXQg+IL4ueef+VSbaOwD0s4MuAZLyKnpzaSpHd6A=; fh=azH8vuUxJaQPgZW4FCAodEWw65A9df1g7DUb4FcTH30=; b=CwsVOO6PExNu+7d2zVwPB4seMDdOFodZzSPpvm5td0TkZXT1Us08ypiJu14n+EFpCH IZu8GSwetxdrMmVymloxmgtBafs4JPCHsu4qW19JntXvNVw/WI3S6uz68WYjW2BIVS4d lg7kXZ/fX759igEVr93bmb+rA7PDoFb9iUxNbYNHdpxt+h6Bgq9OMF+OKlpIQ5f7XVmL XETpBjHJaAg6jjLqGzyCR50U7bVA2laQYJOG56xxH1X1NycKwAa1XKVveu8TRFfrb0vj LP2dkNwcGMCk1Ast35HcEeWXk2Jsh16FLQZL8DuGU/hAdZXsEflq8213A1NtDfzsYA1a mxYA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1 spf=pass spfdomain=dudau.co.uk); spf=pass (google.com: domain of linux-kernel+bounces-111415-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-111415-linux.lists.archive=gmail.com@vger.kernel.org" Return-Path: Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id p2-20020a170906614200b00a46bdfcf233si813783ejl.862.2024.03.22.05.25.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 05:25:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-111415-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=dudau.co.uk); spf=pass (google.com: domain of linux-kernel+bounces-111415-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-111415-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 93FC31F2522C for ; Fri, 22 Mar 2024 12:25:49 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5BA0644C8F; Fri, 22 Mar 2024 12:25:27 +0000 (UTC) Received: from smtp.dudau.co.uk (dliviu.plus.com [80.229.23.120]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B5981446B4; Fri, 22 Mar 2024 12:25:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.229.23.120 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711110326; cv=none; b=aVQUi7tlJ/H+8L1ELnq8mpxgl13dgaPoGYb5nh0cYPrSx9KtycTJ0WJfIsin1nt6GL8BYamOBL6/hXNGDMeOrjZUOPeZpE0homRy91MTRSecfiV/iMEHkxblfoSx97pWi9F89U6KGHqWbAwpdntsqNG3rMIY0jZ+DNVA+L4yO30= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711110326; c=relaxed/simple; bh=JPMHi1XX85jvIDDUVM1CjjE3cn3oHcAZfWVA0Nis8K8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=q5Pc2voLi9yWSoqX+NfMWYmpT6ypxUoFAbUr6nJqIlysFh5qbube4U27UmkcbyDPXzeznhlRgb12PQeMQicXlOJTsayFFZRT6G/2ulyLozIHptjPqQQ3s3qWO6++XgWip+Ns9LBcgm5XHJCRJ5vPTWf8ctIEV6H1TTv+fzxNVys= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=dudau.co.uk; spf=pass smtp.mailfrom=dudau.co.uk; arc=none smtp.client-ip=80.229.23.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=dudau.co.uk Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dudau.co.uk Received: from mail.dudau.co.uk (bart.dudau.co.uk [192.168.14.2]) by smtp.dudau.co.uk (Postfix) with SMTP id 1011B4172F42; Fri, 22 Mar 2024 12:25:20 +0000 (GMT) Received: by mail.dudau.co.uk (sSMTP sendmail emulation); Fri, 22 Mar 2024 12:25:19 +0000 Date: Fri, 22 Mar 2024 12:25:19 +0000 From: Liviu Dudau To: =?utf-8?B?QmrDuHJu?= Mork Cc: Chandrashekar Devegowda , Haijun Liu , Chiranjeevi Rapolu , M Chetan Kumar , Ricardo Martinez , Loic Poulain , Sergey Ryazanov , Johannes Berg , "David S. Miller" , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: net: wwan: t7xx: BUG: Unaligned access when loading mtk_t7xx module Message-ID: References: <87il1ezdbd.fsf@miraculix.mork.no> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87il1ezdbd.fsf@miraculix.mork.no> On Fri, Mar 22, 2024 at 01:00:22PM +0100, Bjørn Mork wrote: > Liviu Dudau writes: > > > I had a > > go at guessing that UL registers are at 0x8 and 0x48 offsets and DL > > registers are at 0x0478 and 0x04b8, but while that fixes the alignment > > exception, I now get a "CLDMA{0,1} queue 0 is not empty" message. > > I don't think you can assume the register offsets are wrong. It looks > more like the device doesn't care about alignment. Sorry, I should clarify: the offsets are wrong when you're trying to do a 64bit read over PCIe for a MEM64 area. Accessed addresses are expected to be multiples of 8 bytes. t7xx_cldma_hw_set_start_addr() uses the offset for the low register for calculating the address for the write, which is not 64bit aligned for the UL block. > > But given that the driver includes , you > can probably replace those unaligned 64bit accesses with two nonatomic > 32bit accesses. > I've tried your suggestion and things seem to progress further, thanks for that! I'm getting some errors on not being able to transition from D3hot to D0, but I guess it might be something to do with the PCIe-to-M.2 adaptor that I'm using. Will continue my investigation into the setup and report back with a patch to replace the register accesses with the lo_hi variants. Best regards, Liviu > > Bjørn -- Everyone who uses computers frequently has had, from time to time, a mad desire to attack the precocious abacus with an axe. -- John D. Clark, Ignition!