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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Fri, 22 Mar 2024 15:19:46 +0200
Message-ID: <CAA8EJpoYBsB8kx8P9w9M3pd6E7iUfqWk4XYwMr2oLoZV_nuYpg@mail.gmail.com>
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8250: add a link between DWC3 and
 QMP PHY
To: "Bryan O'Donoghue" <bryan.odonoghue@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, 
	Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
	Conor Dooley <conor+dt@kernel.org>, linux-arm-msm@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	Luca Weiss <luca.weiss@fairphone.com>
Content-Type: text/plain; charset="UTF-8"

On Fri, 22 Mar 2024 at 14:11, Bryan O'Donoghue
<bryan.odonoghue@linaro.org> wrote:
>
> On 22/03/2024 11:58, Dmitry Baryshkov wrote:
> > The SuperSpeed signals originate from the DWC3 host controller and then
> > are routed through the Combo QMP PHY, where they are multiplexed with
> > the DisplayPort signals. Add corresponding OF graph link.
> >
> > Reported-by: Luca Weiss <luca.weiss@fairphone.com>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >   arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++--
> >   1 file changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index d57039a4c3aa..e551e733ab94 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -3917,6 +3917,10 @@ port@0 {
> >
> >                               port@1 {
> >                                       reg = <1>;
> > +
> > +                                     usb_1_qmpphy_usb_ss_in: endpoint {
> > +                                             remote-endpoint = <&usb_1_dwc3_ss_out>;
> > +                                     };
> >                               };
> >
> >                               port@2 {
> > @@ -4195,8 +4199,24 @@ usb_1_dwc3: usb@a600000 {
> >                               phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> >                               phy-names = "usb2-phy", "usb3-phy";
> >
> > -                             port {
> > -                                     usb_1_dwc3_hs_out: endpoint {};
> > +                             ports {
> > +                                     #address-cells = <1>;
> > +                                     #size-cells = <0>;
> > +
> > +                                     port@0 {
> > +                                             reg = <0>;
> > +
> > +                                             usb_1_dwc3_hs_out: endpoint {
> > +                                             };
> > +                                     };
> > +
> > +                                     port@1 {
> > +                                             reg = <1>;
> > +
> > +                                             usb_1_dwc3_ss_out: endpoint {
> > +                                                     remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
> > +                                             };
> > +                                     };
> >                               };
> >                       };
> >               };
> >
>
> I think these should go into platform definitions, there's nothing at
> the SoC level that imposes the port constraint.

The link between DWC3 and QMP PHY is fixed in the SoC, if I remember correctly.

-- 
With best wishes
Dmitry