Received-SPF: pass (google.com: domain of linux-kernel+bounces-111623-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Date: Fri, 22 Mar 2024 10:32:50 -0400
From: Frank Li <Frank.li@nxp.com>
To: Xu Yang <xu.yang_2@nxp.com>
Cc: will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de,
	festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org,
	namhyung@kernel.org, irogers@google.com, mike.leach@linaro.org,
	peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	imx@lists.linux.dev
Subject: Re: [PATCH v8 5/8] perf: imx_perf: fix counter start and config
 sequence
Message-ID: <Zf2WkluX1WqgBJdL@lizhi-Precision-Tower-5810>
References: <20240322063930.749126-1-xu.yang_2@nxp.com>
 <20240322063930.749126-5-xu.yang_2@nxp.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20240322063930.749126-5-xu.yang_2@nxp.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?MBjuHqY0V2FD6Ewis4G2FydE73sjDxib66I5SjxWR9QsCRN6NBMbXKXCmMdG?=
 =?us-ascii?Q?CTyTfCFbYXhgcyuwNAxSGN5Gg3eXKYmgvFc2PcEB4svEQfAXNnKUSUqsArsK?=
 =?us-ascii?Q?m/y8k5oci4WmWocdr3m/HT41WvR4Tg1aR2SR0QqzjD1K+n+PDDol1bS1DTUr?=
 =?us-ascii?Q?6z1BST1ymDuddB8tWQkEqZjzDeUgeH0rK5M0pD5EqnnLazQWV7pJ3LQrT5tq?=
 =?us-ascii?Q?a85zID9Lr+cPYA2Fj3a65hd0QpIrOGze6PnBcaZYLnNOeDrO6aK1Ir0fvB0v?=
 =?us-ascii?Q?5L41ujMWVIkh8yGIm1/0PZUqidO57v9k2p6e/6PmbAYqsjNMjzI4856Pzdtk?=
 =?us-ascii?Q?pXIbZdaqpPmqghntPiIeRQMftzOgW4miCmX3LjKsEcrwchHeI3RUKtvMvl0e?=
 =?us-ascii?Q?WUw8QU73w+fdi3LA7k9oUjYpyyRhYCmD2HnhQoaNaXmbpoESowCFBdCzt4Po?=
 =?us-ascii?Q?XLe6ZWAn8Eq7kM+hMB1xVzenSCW6+KTFI4iCP9l9VEx81gGczL/0qMmCfnzw?=
 =?us-ascii?Q?IHrlhGeE5FYTrRAo+Y7lXUuNZPco5/6gNhenlEFT1pjNtEdKKQDIXq/qjzI2?=
 =?us-ascii?Q?1NbiT5D7qYkzauAmEHY0ZZG20gE+bl+ElWTbF6iNRmTg7FomJYCmL3p9t1Te?=
 =?us-ascii?Q?Ygcn5BUZ587ZZJ4dWGj8HWfoVKWRQLk2ONnz5h1hCSqC85Ck7w0xuWeQATj6?=
 =?us-ascii?Q?bUW3UBdDgH8ii20WReKlIERptSNpIKY3Nen1jP05Qn4l8+9DCEPJiHrLEgHd?=
 =?us-ascii?Q?K0bHLTgaUvVqkqi2x971+uSFB/R6bfJv644QUwVEbZbyuceVx15mL2sExdZU?=
 =?us-ascii?Q?IrEcJyAHjUygyZx4gOsmBRSdWw5XdtZiMXhMxocibf7VaNGPorWdqbA1FtRi?=
 =?us-ascii?Q?X20wbWcs5GwbZ+fi7pTpUoh8mm7CSl3/4nXsmTuwB+HfDbiAO73gbrLZXQcb?=
 =?us-ascii?Q?TAYY3TsN8A3qCw/wN3XjOK17zNv6qZW4n+IQRexsRb8b9DVIbWmINVuRDZVT?=
 =?us-ascii?Q?ZQXnVojQW9iLpDLcy4rK5jrt5GqBNreA8cxDuSDdbOscgKQHeCWPjD/7JlK+?=
 =?us-ascii?Q?zFfOAJO1suTe8x2o0QNSpHeH+oimEYb/wATIZ6gX+8OPwPDPRgbC37laxMA0?=
 =?us-ascii?Q?qyJ49balHf+GARCf4PjBr2hAxpyCCyWGM1QRGGu3USyt8JFAqTuIVWKUkP0C?=
 =?us-ascii?Q?MRkkLsPs9O8mhAyoLnLLQsNfz9EkuLUUPhpeMjJ7otwkp8Dgse5YNBDuHinj?=
 =?us-ascii?Q?QEEF6qaGZkCemBGMf4Zc1NtB0NjHwoqNaKeXYIZLhcXpXvjpyQ3j9h4aBxGS?=
 =?us-ascii?Q?hC7xO9pWOBA1uV3GXDsQwg76E0ztqL9FVrAFaT1M9Xfe9De+nNsG5wkMomWW?=
 =?us-ascii?Q?bGwoevoYlbx8CbRxeX+WzuuNR6CSW4rZPI8sNWGSvLqEGMJq46zjg5Kt96BY?=
 =?us-ascii?Q?857y2FPBp5GRLP/oM3gaqDl0IRp8IGb+GQG6QFtzCpGTz6tWtfvZx1zi5lvl?=
 =?us-ascii?Q?WwUIe5M2UQ/uS8he+ulU4Ea/oAPJK/8Gg5LFs2+t9HBIFZc+Gq4fGucZQdBQ?=
 =?us-ascii?Q?OZDVdIaALSc74Krb+zE=3D?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 6df4c0df-0340-4314-8732-08dc4a7cf9b7
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2024 14:33:00.7351
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: hUTqfcLlubDzMq2qAa7qpcc8xgNgfhIyhJh8DZyTS3Hfl4J8eYww5T9AIDRacjkaFQk+/OQnxfPLby2b3kvCQw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8707

On Fri, Mar 22, 2024 at 02:39:27PM +0800, Xu Yang wrote:
> In current driver, the counter will start firstly and then be configured.
> This sequence is not correct for AXI filter events since the correct
> AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.
> 
> Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
> cc: <stable@vger.kernel.org>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> 
> ---
> Changes in v5:
>  - new patch
> Changes in v6:
>  - no changes
> Changes in v7:
>  - no changes
> Changes in v8:
>  - add fix tag
> ---
>  drivers/perf/fsl_imx9_ddr_perf.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
> index 011377c01dea..fab6596d3e28 100644
> --- a/drivers/perf/fsl_imx9_ddr_perf.c
> +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> @@ -539,12 +539,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
>  	hwc->idx = counter;
>  	hwc->state |= PERF_HES_STOPPED;
>  
> -	if (flags & PERF_EF_START)
> -		ddr_perf_event_start(event, flags);
> -
>  	/* read trans, write trans, read beat */
>  	imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
>  
> +	if (flags & PERF_EF_START)
> +		ddr_perf_event_start(event, flags);
> +
>  	return 0;
>  }
>  
> -- 
> 2.34.1
>