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Date: Fri, 22 Mar 2024 17:03:08 +0100
Message-Id: <D00EM8TTYGXL.3MMIBWJT03M5R@baylibre.com>
Subject: Re: [PATCH v4 10/11] pinctrl: pinctrl-tps6594: Add TPS65224 PMIC
 pinctrl and GPIO
From: "Esteban Blanc" <eblanc@baylibre.com>
To: "Bhargav Raviprakash" <bhargav.r@ltts.com>,
 <linux-kernel@vger.kernel.org>
Cc: <m.nirmaladevi@ltts.com>, <lee@kernel.org>, <robh+dt@kernel.org>,
 <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
 <jpanis@baylibre.com>, <devicetree@vger.kernel.org>, <arnd@arndb.de>,
 <gregkh@linuxfoundation.org>, <lgirdwood@gmail.com>, <broonie@kernel.org>,
 <linus.walleij@linaro.org>, <linux-gpio@vger.kernel.org>,
 <linux-arm-kernel@lists.infradead.org>, <nm@ti.com>, <vigneshr@ti.com>,
 <kristo@kernel.org>
References: <20240320102559.464981-1-bhargav.r@ltts.com>
 <20240320102559.464981-11-bhargav.r@ltts.com>
In-Reply-To: <20240320102559.464981-11-bhargav.r@ltts.com>

On Wed Mar 20, 2024 at 11:25 AM CET, Bhargav Raviprakash wrote:
> From: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
>
> Add support for TPS65224 pinctrl and GPIOs to TPS6594 driver as they have
> significant functional overlap.
> TPS65224 PMIC has 6 GPIOS which can be configured as GPIO or other
> dedicated device functions.
>
> Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
> Signed-off-by: Bhargav Raviprakash <bhargav.r@ltts.com>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/pinctrl/pinctrl-tps6594.c | 258 +++++++++++++++++++++++++-----
>  1 file changed, 215 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-=
tps6594.c
> index 66985e54b..db0f5d2a8 100644
> --- a/drivers/pinctrl/pinctrl-tps6594.c
> +++ b/drivers/pinctrl/pinctrl-tps6594.c
> @@ -320,8 +451,18 @@ static int tps6594_pinctrl_probe(struct platform_dev=
ice *pdev)
>  		return -ENOMEM;
>  	pctrl_desc->name =3D dev_name(dev);
>  	pctrl_desc->owner =3D THIS_MODULE;
> -	pctrl_desc->pins =3D tps6594_pins;
> -	pctrl_desc->npins =3D ARRAY_SIZE(tps6594_pins);
> +	switch (tps->chip_id) {
> +	case TPS65224:
> +		pctrl_desc->pins =3D tps65224_pins;
> +		pctrl_desc->npins =3D ARRAY_SIZE(tps65224_pins);
> +		break;
> +	case TPS6594:
> +		pctrl_desc->pins =3D tps6594_pins;
> +		pctrl_desc->npins =3D ARRAY_SIZE(tps6594_pins);
> +		break;
> +	default:
> +		break;
> +	}
>  	pctrl_desc->pctlops =3D &tps6594_pctrl_ops;
>  	pctrl_desc->pmxops =3D &tps6594_pmx_ops;

See below.

> @@ -329,8 +470,28 @@ static int tps6594_pinctrl_probe(struct platform_dev=
ice *pdev)
>  	if (!pinctrl)
>  		return -ENOMEM;
>  	pinctrl->tps =3D dev_get_drvdata(dev->parent);
> -	pinctrl->funcs =3D pinctrl_functions;
> -	pinctrl->pins =3D tps6594_pins;
> +	switch (pinctrl->tps->chip_id) {

You could use tps->chip_id like in the previous switch.

> +	case TPS65224:
> +		pinctrl->funcs =3D tps65224_pinctrl_functions;
> +		pinctrl->func_cnt =3D ARRAY_SIZE(tps65224_pinctrl_functions);
> +		pinctrl->pins =3D tps65224_pins;
> +		pinctrl->num_pins =3D ARRAY_SIZE(tps65224_pins);
> +		pinctrl->mux_sel_mask =3D TPS65224_MASK_GPIO_SEL;
> +		pinctrl->remap =3D tps65224_muxval_remap;
> +		pinctrl->remap_cnt =3D ARRAY_SIZE(tps65224_muxval_remap);
> +		break;
> +	case TPS6594:
> +		pinctrl->funcs =3D pinctrl_functions;

This should be tps6594_pinctrl_functions

> +		pinctrl->func_cnt =3D ARRAY_SIZE(pinctrl_functions);
> +		pinctrl->pins =3D tps6594_pins;
> +		pinctrl->num_pins =3D ARRAY_SIZE(tps6594_pins);
> +		pinctrl->mux_sel_mask =3D TPS6594_MASK_GPIO_SEL;
> +		pinctrl->remap =3D tps6594_muxval_remap;
> +		pinctrl->remap_cnt =3D ARRAY_SIZE(tps6594_muxval_remap);
> +		break;
> +	default:
> +		break;
> +	}

See blow.

>  	pinctrl->pctl_dev =3D devm_pinctrl_register(dev, pctrl_desc, pinctrl);
>  	if (IS_ERR(pinctrl->pctl_dev))
>  		return dev_err_probe(dev, PTR_ERR(pinctrl->pctl_dev),
> @@ -338,8 +499,18 @@ static int tps6594_pinctrl_probe(struct platform_dev=
ice *pdev)
> =20
>  	config.parent =3D tps->dev;
>  	config.regmap =3D tps->regmap;
> -	config.ngpio =3D TPS6594_PINCTRL_PINS_NB;
> -	config.ngpio_per_reg =3D 8;
> +	switch (pinctrl->tps->chip_id) {

Same here, use tps->chip_id

> +	case TPS65224:
> +		config.ngpio =3D ARRAY_SIZE(tps65224_gpio_func_group_names);
> +		config.ngpio_per_reg =3D TPS65224_NGPIO_PER_REG;
> +		break;
> +	case TPS6594:
> +		config.ngpio =3D ARRAY_SIZE(tps6594_gpio_func_group_names);
> +		config.ngpio_per_reg =3D TPS6594_NGPIO_PER_REG;
> +		break;
> +	default:
> +		break;
> +	}
>  	config.reg_dat_base =3D TPS6594_REG_GPIO_IN_1;
>  	config.reg_set_base =3D TPS6594_REG_GPIO_OUT_1;
>  	config.reg_dir_out_base =3D TPS6594_REG_GPIOX_CONF(0);

Regarding all the switch case, they should be use to set all the struct
fields that are known at runtime only. For example, pinctrl->funcs, and
pinctrl->func_cnt are known at compile time. You should create template
structs, one for TPS6594 the other TPS65224, initialise the allocated
struct with the template and then fill the remaining fields with the
runtime values. Something like this:

```c
struct test {
    int a;
    int *b;
};

static struct test template =3D {
    .a =3D 42,
};

int main(void) {
    struct test *test =3D malloc(sizeof(*test));
    *test =3D sample;
    test->b =3D NULL;

    return 0;
}
```

You could also try to reduce the number of switch case, there is no good
reason to have 2 switch instead of one for pctrl_desc and pinctrl
structs.

Best regards,

--=20
Esteban "Skallwar" Blanc
BayLibre