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AJvYcCXbkWnosz7RmycRqq3StO7NxIYguxZVqQrV70g0/0TWx6xgf5VNXdtd7YEo0/MI7+PJpi6erDjzWFzvd4QGBzxbgUcYW1Jy9mv3b98e X-Gm-Message-State: AOJu0YwkndnlNhfDg2GTHTTgVOHlhR3FCbRKEYDlYNPd5I/N4jHqcUHN jUzmOw8/FsslqduKmgc7x2RZymnS2G5soFbdok8T3i8bAWP943JuyN9hgk0k1oiy2p9vEWQ6mYM B4FcsD80n64W2eq/n57v4QjFuvWI= X-Received: by 2002:a17:90a:b395:b0:2a0:350a:a7a8 with SMTP id e21-20020a17090ab39500b002a0350aa7a8mr123918pjr.2.1711124958335; Fri, 22 Mar 2024 09:29:18 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240322130646.1016630-1-marcel@ziswiler.com> In-Reply-To: <20240322130646.1016630-1-marcel@ziswiler.com> From: Fabio Estevam Date: Fri, 22 Mar 2024 13:29:05 -0300 Message-ID: Subject: Re: [PATCH v1 0/1] phy: freescale: imx8m-pcie: facing pcie link-up instability To: Marcel Ziswiler Cc: linux-phy@lists.infradead.org, linux-imx@nxp.com, Lucas Stach , linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, Richard Zhu , linux-kernel@vger.kernel.org, Marcel Ziswiler , Heiko Stuebner , Kishon Vijay Abraham I , Marc Kleine-Budde , Rob Herring , Sascha Hauer , Shawn Guo , Tim Harvey , Vinod Koul , Yang Li , imx@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Marcel, On Fri, Mar 22, 2024 at 10:07=E2=80=AFAM Marcel Ziswiler wrote: > > From: Marcel Ziswiler > > > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > While this setup has proven very stable overall we noticed upstream on > the i.MX8M Mini fails quite regularly (about 50/50) to bring up the PCIe > link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. As > that old downstream stuff was quite different, I first also tried NXP's > latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view is > fairly vanilla, however, also there the PCIe link-up was not stable. > Comparing and debugging I noticed that upstream explicitly configures > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > Unfortunately, the TRM does not mention any further details about this > register (both for the i.MX 8M Mini as well as the Plus). Maybe somebody > from NXP could further comment on this? > > BTW: On the i.MX 8M Plus we have not seen any issues with PCIe with the > exact same setup which is why I left it unchanged. > > [1] https://www.delock.com/produkt/95233/merkmale.html > [2] https://github.com/nxp-imx/linux-imx/blob/lf-5.15.71-2.2.0/drivers/pc= i/controller/dwc/pci-imx6.c#L1548 The detailed information above is important. It should be in the commit log of the patch IMHO. Thanks for the fix.