Received-SPF: pass (google.com: domain of linux-kernel+bounces-111800-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
From: Frank Li <Frank.Li@nxp.com>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	Dong Aisheng <aisheng.dong@nxp.com>,
	devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS),
	imx@lists.linux.dev (open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 1/1] arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock order
Date: Fri, 22 Mar 2024 12:47:05 -0400
Message-Id: <20240322164706.2626088-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?uW01BKcEzHzegBJC+e7UjxBY0+xNpFFnacIfq8Y0xiYdWTKzGdjv5d6k2MDy?=
 =?us-ascii?Q?wQVHGFFJJkEF4Vwe8ezzrCWX/ZnVrZ6aFVR3vHAqePJS4/bJWH/p0TkvkAkf?=
 =?us-ascii?Q?4aENNDw46K8a3ci1w8t0KiXVdqKXztzTUle3JHGWhgEr5OpM5/Ce5jSVh8lx?=
 =?us-ascii?Q?KFJSxhMqpNAvvXwaU9ThLacwTnoRaRVVo0W/h1XcR5Gwcfn6/bEhD+b/U5RS?=
 =?us-ascii?Q?Kav9NHgdv+aOW74lOshQlQ7EZJsjblgK3h9ZRe6USzsdfYfMA/Z1h9KSGjqp?=
 =?us-ascii?Q?0lKYXDGeRBaGILqtJxf81bZf4nyOV/5I7+H5JPti5MdtDqmzDdeOIkhfgRhL?=
 =?us-ascii?Q?dDvBPifdQtvv/jwMQo9Utw+tBULUdOj4UrPYU0KTtHefVXEJTy3SkzEyYJA/?=
 =?us-ascii?Q?/XOqJ21qPT4oANT7LCeTx3sAOw1ljC6eUoo79QJZ6ZwCOWOK2tWVJRQ+bz4k?=
 =?us-ascii?Q?wqPNwND0Ew2aCUxwQ5d28h7P8h6TVFGPXxTa1+/8zVeDFBYUhGQMeAY8ypER?=
 =?us-ascii?Q?e9rgP2RXEu7YcOL/BFE2dCvk66czvCLDJ4k7DmrCfKU8WsXqkhLDQOMcNKtT?=
 =?us-ascii?Q?0mRIeE8Q+6rHdVP59MrpBSmYP6lC8znYDFe1VVudVxM1n+blVKyTHBrMf4qn?=
 =?us-ascii?Q?3qm1F8NkdfIVAmZ36MbROLjI9MRFU5vl4IOuECKfP8kBzJLKg+AaBySFxgNR?=
 =?us-ascii?Q?vblUPK66bHj/6BrieIB+YXS6w2V4xC+3kXRo1UAyWMPLgjCKoHJGzfC1lixg?=
 =?us-ascii?Q?bXBKvdlTLN5QNJ4vfcqPZphrOAPWI3HLqE7wIPnL87EMwZfcycc1UvZdFPCz?=
 =?us-ascii?Q?XD5gG8jAb8xCn158jjm2lwB36Xp6k82WVrQHvMZ+mr0S+vbRMVEcFdp1RbOJ?=
 =?us-ascii?Q?f3TeJ1EAcEX14WP19ss7Y1ies8Xhd8V8AGIVxsbo7loyZfwUr1u3CgMb49Q5?=
 =?us-ascii?Q?sqR6Tq/7XefFr8VN2sduoHTNhfQw1RkM+rqf7SozRGN4Z1fZOP2pOjcC1X36?=
 =?us-ascii?Q?vgzt1Rixhy5MWCzyuj2uam9+zIOUWrT5suYo+TTOyFds0S8FqRcUuczncRJa?=
 =?us-ascii?Q?mkGUSgrM1xRm/7Mqw1V1O2jx8dnPhd/ddr1HFimEmcFTs4PtkP8QxrhphtlF?=
 =?us-ascii?Q?uXFQvNyNMsQ3j3AenO/cJSS6UIq1HqtZ6h9Z754gv1cYfKZmBlA5NUFZNbii?=
 =?us-ascii?Q?r22ST7KISzdYhzSTsmABlWalzFL5OXdBcxfmiIB+v43z2RBLTF2OoPVjlT8a?=
 =?us-ascii?Q?tPk4a/Z7EaAmu8zY/fKbDFRnZZpa4vYiRijQXqnPoT7D+fEpvIyivnKjnTuz?=
 =?us-ascii?Q?k5vxDbl1ilJ7MMzV4+TvvwJ+arLvyxnewFu+Ovc63TmSX7k1y59w24Iz3RHd?=
 =?us-ascii?Q?f1GgudpxVhUhthq3HfyUFNda3ZPBRjnIAHyJe7ALWOZYCUpTEjnY3YaNx5TZ?=
 =?us-ascii?Q?qQK4PQtJOraOLxOckA6b7mEHiI5EvaHWVBAcKEggA4qZzP9U6QvnsEcRjpa4?=
 =?us-ascii?Q?a5kGj0pCixqqF0aYuGbkxHyl+AY8TQ01AeWAf7R4H8R7XIpabog+gQxi5SFT?=
 =?us-ascii?Q?bK6zLHZAxBr77XV/6xGvFiCxjVc47Gg2PaUovo/Q?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: e775c2ae-d62a-47e1-e868-08dc4a8fbd8b
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2024 16:47:20.2334
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 6jbcFlFBYJp4yPhgTH85LE7VsjRKSOo2DYphe3Ly0uSdPAxYupI46paYhodLmiqdP/Q9K6UHzhGNlKqzVejwUA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7477

The actual clock show wrong frequency:

   echo on >/sys/devices/platform/bus\@5b000000/5b010000.mmc/power/control
   cat /sys/kernel/debug/mmc0/ios

   clock:          200000000 Hz
   actual clock:   166000000 Hz
                   ^^^^^^^^^
   .....

According to

sdhc0_lpcg: clock-controller@5b200000 {
                compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5b200000 0x10000>;
                #clock-cells = <1>;
                clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
                         <&conn_ipg_clk>, <&conn_axi_clk>;
                clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
                                <IMX_LPCG_CLK_5>;
                clock-output-names = "sdhc0_lpcg_per_clk",
                                     "sdhc0_lpcg_ipg_clk",
                                     "sdhc0_lpcg_ahb_clk";
                power-domains = <&pd IMX_SC_R_SDHC_0>;
        }

"per_clk" should be IMX_LPCG_CLK_0 instead of IMX_LPCG_CLK_5.

After correct clocks order:

   echo on >/sys/devices/platform/bus\@5b000000/5b010000.mmc/power/control
   cat /sys/kernel/debug/mmc0/ios

   clock:          200000000 Hz
   actual clock:   198000000 Hz
                   ^^^^^^^^
   ...

Fixes: 16c4ea7501b1 ("arm64: dts: imx8: switch to new lpcg clock binding")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 3c42240e78e24..af2259e997967 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -67,8 +67,8 @@ usdhc1: mmc@5b010000 {
 		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0x5b010000 0x10000>;
 		clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
-			 <&sdhc0_lpcg IMX_LPCG_CLK_0>,
-			 <&sdhc0_lpcg IMX_LPCG_CLK_5>;
+			 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
+			 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
 		power-domains = <&pd IMX_SC_R_SDHC_0>;
 		status = "disabled";
@@ -78,8 +78,8 @@ usdhc2: mmc@5b020000 {
 		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0x5b020000 0x10000>;
 		clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
-			 <&sdhc1_lpcg IMX_LPCG_CLK_0>,
-			 <&sdhc1_lpcg IMX_LPCG_CLK_5>;
+			 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
+			 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
 		power-domains = <&pd IMX_SC_R_SDHC_1>;
 		fsl,tuning-start-tap = <20>;
@@ -91,8 +91,8 @@ usdhc3: mmc@5b030000 {
 		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 		reg = <0x5b030000 0x10000>;
 		clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
-			 <&sdhc2_lpcg IMX_LPCG_CLK_0>,
-			 <&sdhc2_lpcg IMX_LPCG_CLK_5>;
+			 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
+			 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
 		power-domains = <&pd IMX_SC_R_SDHC_2>;
 		status = "disabled";
-- 
2.34.1