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AJvYcCVKjOS2R1fJ2xLBFrxk0nSwqdfEDMWllC0R/fDtxdemYIdizkxEaR3/whwgKJEXoFDkTA/zQlGng0nl90HqDfcwHOMS6akTBBUaIljD X-Gm-Message-State: AOJu0Yz3qtIrd5YayLFe4FaUZgQlhSP3nj/MsoD5Sw/rJgttMQGSa4x+ kuGCPxK30Xj/Qsu8XFgtVDk44sCDQw1ijUa+adGdq4C1pozJ5j0ehQ0Q5SKItva7g0vTNRum61L gAt3CHqAG2rp/I11P2BIIqeHa/rAxq1V7GOvNk1USG9ytiYUOTro= X-Received: by 2002:a17:90a:6d61:b0:29c:b540:706b with SMTP id z88-20020a17090a6d6100b0029cb540706bmr424792pjj.17.1711130988988; Fri, 22 Mar 2024 11:09:48 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240229122021.1901785-1-tudor.ambarus@linaro.org> <20240229122021.1901785-5-tudor.ambarus@linaro.org> <867158d7-0d98-4058-9c2e-6b573ec68516@linaro.org> In-Reply-To: <867158d7-0d98-4058-9c2e-6b573ec68516@linaro.org> From: Sam Protsenko Date: Fri, 22 Mar 2024 13:09:37 -0500 Message-ID: Subject: Re: [PATCH 4/4] clk: samsung: exynos850: fix propagation of SPI IPCLK rate To: Tudor Ambarus Cc: =?UTF-8?B?6rmA7J6s7JuQL0pBRVdPTiBLSU0=?= , krzysztof.kozlowski@linaro.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, peter.griffin@linaro.org, andre.draszik@linaro.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Mar 22, 2024 at 4:39=E2=80=AFAM Tudor Ambarus wrote: > > Hi, Sam! > > On 3/1/24 00:13, Sam Protsenko wrote: > > I fail to see how this patch fixes anything. Instead it looks to me it > > replaces the (already) correctly implemented logic with incorrect one. > > I opened another thread asking for feedback on whether it's safe to > re-parent the USI MUX to OSCCLK at run-time, find it here: > https://lore.kernel.org/linux-samsung-soc/71df1d6b-f40b-4896-a672-c5f0f52= 6fb1f@linaro.org/T/#m588abb87eb5fd8817d71d06b94c91eb84928e06b > > Jaewon came up with the idea on verifying what the downstream clock > driver does. I added some prints in the driver, and indeed the USI MUX > re-parents to OSCCLK on low SPI clock rates in the GS101 case. > > Thus I'll respin this patch set fixing GS101 on low USI clock rates by > re-parenting the USI MUX to OSCCLK. I'll leave exynos850 out if I don't > hear back from you, but I think it deserves the same fix. Allowing SPI > to modify the clock rate of HSI2C/I3C at run-time is bad IMO. > Re-parenting the USI MUX to OSCCLK fixes this problem, HSI2C/I3C will no > longer be affected on low SPI clock rates. > Yes, please leave Exynos850 out of it, if possible. It's fine with me if you send it for gs101, as it's you who is going to maintain that platform further, so it's for the maintainers to decide. I'll refrain from reviewing that particular patch. For Exynos850 driver, I'm convinced the SPI clock derivation is already implemented in the correct way (exactly as it was designed in HW), and doing anything else would be a hack, and frankly this sole fact is already enough of argumentation for me. There is also the whole bunch of use-cases which I think could be affected by using OSCCLK, e.g.: clock signal integrity, runtime PM concerns, possible interference in case of automatic clock control enablement, etc. I don't even want to think about all possible pitfalls which implementation of this non-standard and undocumented behavior could create. So as the only person who currently supports Exynos850 drivers (apart from the maintainers, of course), I would strictly oppose this particular OSCCLK change. > Cheers, > ta