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Message-ID: <4bc4c4d1-f2b3-4b08-a211-0b05c5838ef0@linaro.org>
Date: Sat, 23 Mar 2024 01:24:54 +0100
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Subject: Re: [PATCH v2 3/3] PCI: qcom: Add rx margining settings for gen4
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To: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>,
 agross@kernel.org, andersson@kernel.org, mani@kernel.org
Cc: quic_msarkar@quicinc.com, quic_kraravin@quicinc.com,
 Lorenzo Pieralisi <lpieralisi@kernel.org>,
 =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
 Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
 Jingoo Han <jingoohan1@gmail.com>,
 Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
 Serge Semin <fancer.lancer@gmail.com>,
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
 Conor Dooley <conor.dooley@microchip.com>, linux-kernel@vger.kernel.org,
 linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org
References: <20240320071527.13443-1-quic_schintav@quicinc.com>
 <20240320071527.13443-4-quic_schintav@quicinc.com>
From: Konrad Dybcio <konrad.dybcio@linaro.org>
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In-Reply-To: <20240320071527.13443-4-quic_schintav@quicinc.com>
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On 20.03.2024 08:14, Shashank Babu Chinta Venkata wrote:
> Add rx margining settings for gen4 operation.

Why are these necessary? What do they change?

> 
> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.h | 23 +++++++++++++
>  drivers/pci/controller/dwc/pcie-qcom-cmn.c   | 35 ++++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-qcom-cmn.h   | 11 +++++-
>  drivers/pci/controller/dwc/pcie-qcom-ep.c    |  4 ++-
>  drivers/pci/controller/dwc/pcie-qcom.c       |  4 ++-
>  5 files changed, 74 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 064744bfe35a..ce1c5f9c406a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -206,6 +206,29 @@
>  
>  #define PCIE_PL_CHK_REG_ERR_ADDR			0xB28
>  
> +/*
> + * GEN4 lane margining register definitions
> + */
> +#define GEN4_LANE_MARGINING_1_OFF		0xb80
> +#define MARGINING_MAX_VOLTAGE_OFFSET_MASK	GENMASK(29, 24)
> +#define MARGINING_NUM_VOLTAGE_STEPS_MASK	GENMASK(22, 16)
> +#define MARGINING_MAX_TIMING_OFFSET_MASK	GENMASK(13, 8)
> +#define MARGINING_NUM_TIMING_STEPS_MASK		GENMASK(5, 0)
> +#define MARGINING_MAX_VOLTAGE_OFFSET_SHIFT	24
> +#define MARGINING_NUM_VOLTAGE_STEPS_SHIFT	16
> +#define MARGINING_MAX_TIMING_OFFSET_SHIFT	8
> +
> +#define GEN4_LANE_MARGINING_2_OFF		0xb84

The file

drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h

defines registers with exactly the same names at exacly the same offsets.

If this is a DWC-common thing, it should go to DWC-common code.

Konrad