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(unknown [IPv6:240e:358:11fe:a000:dc73:854d:832e:8]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id EA8A0668E6; Sun, 24 Mar 2024 15:05:44 -0400 (EDT) From: Xi Ruoyao To: Dave Hansen Cc: Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, Xi Ruoyao Subject: [PATCH v2] x86/mm: Don't disable INVLPG if "incomplete Global INVLPG flushes" is fixed by microcode Date: Mon, 25 Mar 2024 03:05:03 +0800 Message-ID: <20240324190503.116160-1-xry111@xry111.site> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Per the "Processor Specification Update" documentations referred by the intel-microcode-20240312 release note, this microcode release has fixed the issue for all affected models. So don't disable INVLPG if the microcode is new enough. Cc: Dave Hansen Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/ Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20240312 Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 Signed-off-by: Xi Ruoyao --- arch/x86/mm/init.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 679893ea5e68..c52be4e66e44 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -261,33 +261,41 @@ static void __init probe_page_size_mask(void) } } -#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ - .family = 6, \ - .model = _model, \ - } +#define INTEL_MATCH(_model, _fixed_microcode) \ + { .vendor = X86_VENDOR_INTEL, \ + .family = 6, \ + .model = _model, \ + .driver_data = _fixed_microcode, \ + } + /* * INVLPG may not properly flush Global entries - * on these CPUs when PCIDs are enabled. + * on these CPUs when PCIDs are enabled and the + * microcode is not updated to fix the issue. */ static const struct x86_cpu_id invlpg_miss_ids[] = { - INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), - INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), - INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT ), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), - INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE, 0x34), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L, 0x432), + INTEL_MATCH(INTEL_FAM6_ATOM_GRACEMONT, 0x15), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE, 0x122), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P, 0x4121), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S, 0x34), {} }; static void setup_pcid(void) { + const struct x86_cpu_id *invlpg_miss_match; + if (!IS_ENABLED(CONFIG_X86_64)) return; if (!boot_cpu_has(X86_FEATURE_PCID)) return; - if (x86_match_cpu(invlpg_miss_ids)) { + invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); + if (invlpg_miss_match && + invlpg_miss_match->driver_data > boot_cpu_data.microcode) { pr_info("Incomplete global flushes, disabling PCID"); setup_clear_cpu_cap(X86_FEATURE_PCID); return; -- 2.44.0