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[209.132.180.67]) by mx.google.com with ESMTP id f22si11176108pli.501.2017.10.12.04.00.28; Thu, 12 Oct 2017 04:00:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755575AbdJLK7q (ORCPT + 99 others); Thu, 12 Oct 2017 06:59:46 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:8011 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755204AbdJLK7p (ORCPT ); Thu, 12 Oct 2017 06:59:45 -0400 Received: from 172.30.72.59 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIZ62644; Thu, 12 Oct 2017 18:59:34 +0800 (CST) Received: from [127.0.0.1] (10.177.17.188) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.301.0; Thu, 12 Oct 2017 18:58:36 +0800 Subject: Re: [PATCH 0/2] arm64 SMMUv3 PMU driver with IORT support To: "Leeder, Neil" , Hanjun Guo , Will Deacon , Mark Rutland References: <1501876754-1064-1-git-send-email-nleeder@codeaurora.org> <394bd3b8-2583-01fa-02d3-6a49c2a6a6c0@linaro.org> <3eac1295-dba2-ad79-d868-b538b13de91a@codeaurora.org> <67a696ad-98e9-d505-1d73-7246d2efc398@codeaurora.org> CC: , , Mark Langsdorf , Mark Salter , "Jon Masters" , Timur Tabi , Mark Brown , Lorenzo Pieralisi , "Robin Murphy" From: Hanjun Guo Message-ID: <59DF4AD9.2060903@huawei.com> Date: Thu, 12 Oct 2017 18:58:33 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <67a696ad-98e9-d505-1d73-7246d2efc398@codeaurora.org> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.177.17.188] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59DF4B17.0079,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ccce072dbd4cc682e68a7d14aec849f0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2017/8/11 11:28, Leeder, Neil wrote: > On 8/9/2017 9:26 PM, Hanjun Guo wrote: >> > On 2017/8/9 23:48, Leeder, Neil wrote: >>>>> >>>> drivers/perf/Kconfig | 9 + >>>>> >>>> drivers/perf/Makefile | 1 + >>>>> >>>> drivers/perf/arm_smmuv3_pmu.c | 823 ++++++++++++++++++++++++++++++++++++++++++ >>>>> >>>> include/acpi/actbl2.h | 9 +- >>>> >>> Do you have the acpica support code? I'm currently >>>> >>> working on SMMUv3 MSI support and I would like to test >>>> >>> it with MSI support for PMCG as well. >>> >> I don't have any code other than what was posted here. >>> >> What additional ACPICA support code is needed? >> > >> > Sorry for not clear, I mean the acpica code for iASL and >> > other tool: github.com/acpica/acpica.git >> > >> > With that code, I can compile my IORT table with PMCG node. > Unfortunately it looks like I'm the first person from Qualcomm Datacenter > Technologies to try to add something to ACPICA, which means I'll have to > kick off an internal legal process which may take some time. Unless someone > else wants to take a crack at it - and really, there's nothing more than is > in the ARM IORT spec - it could be a while before I can do that. Just a update, I sent a pull request to Bob for ACPICA changes, please take a look: https://github.com/acpica/acpica/pull/327 Thanks Hanjun From 1575403800924822039@xxx Fri Aug 11 03:29:02 +0000 2017 X-GM-THRID: 1574831973672201036 X-Gmail-Labels: Inbox,Category Forums