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[209.132.180.67]) by mx.google.com with ESMTP id y22si26045424pfe.78.2017.11.27.19.51.16; Mon, 27 Nov 2017 19:51:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753658AbdK1DuS (ORCPT + 77 others); Mon, 27 Nov 2017 22:50:18 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:55869 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752743AbdK1DuM (ORCPT ); Mon, 27 Nov 2017 22:50:12 -0500 X-UUID: ac13865666b340f394ee8f0d6a523b59-20171128 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1118434087; Tue, 28 Nov 2017 11:50:07 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 28 Nov 2017 11:50:04 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 28 Nov 2017 11:50:04 +0800 From: To: , , , , , CC: , , , Sean Wang Subject: [PATCH 0/4] add support of pinctrl to MT7622 SoC Date: Tue, 28 Nov 2017 11:49:58 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Wang The patchset adds support for pinctrl on MT7622 SoC. patch 1: describe the hardware, also including the defintion for pins, groups and function. patch 2: add cleanup for keep drivers inside the independent menu. patch 3/4: add support for mt7622 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. However, the IO core for the MT7622 SoC is completely distinct from anyone of previous MediaTek SoCs which already had support, such as the hardware internal, register address map and register detailed definition for each pin. Therefore, instead, the driver is being newly implemented by reusing generic methods provided from the core layer with GENERIC_PINCONF, GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code simplicity and avoiding superfluous code. Where the function of pins determined by groups is utilized in this driver which can help developers less confused with what combinations of pins effective on the SoC and even reducing the mistakes during the integration of those relevant boards. As the gpio_chip handling is also only a few lines, the driver also implements the gpio functionality directly through GPIOLIB. Sean Wang (4): dt-bindings: pinctrl: add bindings for MediaTek MT7622 SoC pinctrl: mediatek: cleanup for placing all drivers under the menu pinctrl: mediatek: add pinctrl driver for MT7622 SoC pinctrl: mediatek: update MAINTAINERS entry with MediaTek pinctrl driver .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 330 +++++ MAINTAINERS | 10 + drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/mediatek/Kconfig | 15 +- drivers/pinctrl/mediatek/Makefile | 3 +- drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1536 ++++++++++++++++++++ 6 files changed, 1892 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c -- 2.7.4 From 1585552562230585760@xxx Fri Dec 01 03:59:15 +0000 2017 X-GM-THRID: 1585552562230585760 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread