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[209.132.180.67]) by mx.google.com with ESMTP id i74si24082619pgc.832.2017.11.27.22.41.36; Mon, 27 Nov 2017 22:41:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751427AbdK1Gjl (ORCPT + 77 others); Tue, 28 Nov 2017 01:39:41 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:57343 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751163AbdK1Gjj (ORCPT ); Tue, 28 Nov 2017 01:39:39 -0500 X-UUID: 3a4969e5a7654aab93f1bbbe2ec74b13-20171128 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 492426108; Tue, 28 Nov 2017 14:39:33 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 28 Nov 2017 14:39:26 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 28 Nov 2017 14:39:26 +0800 Message-ID: <1511851166.28444.1.camel@mtkswgap22> Subject: Re: [PATCH v7 1/1] pwm: mediatek: add MT2712/MT7622 support From: Sean Wang To: Zhi Mao CC: , Thierry Reding , , Rob Herring , "Mark Rutland" , Matthias Brugger , , , , , , , , , Date: Tue, 28 Nov 2017 14:39:26 +0800 In-Reply-To: <1510576744.12324.23.camel@mhfsdcap03> References: <1508926261-25015-1-git-send-email-zhi.mao@mediatek.com> <1510576744.12324.23.camel@mhfsdcap03> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Zhi The patch have already got merged in 4.15 rc1 as https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=424268c7494c2ae24c95565b9047bbf30309e88a Sean On Mon, 2017-11-13 at 20:39 +0800, Zhi Mao wrote: > Hi Thierry, > > Just have a ping for this patch. > > Regards > Zhi > > > On Wed, 2017-10-25 at 18:11 +0800, Zhi Mao wrote: > > Add support to MT2712 and MT7622. > > Due to register offset address of pwm7 for MT2712 is not fixed 0x40, > > add mtk_pwm_reg_offset array for pwm register offset. > > > > Reviewed-by: Claudiu Beznea > > Reviewed-by: Matthias Brugger > > Signed-off-by: Zhi Mao > > --- > > changee in v7: > > - adjust the commit message > > > > Changes in v6: > > - remove "struct mtk_pwm_platform_data" member from "mtk_pwm_chip". > > > > Changes in v5: > > - Add NULL pointer checking for "data" > > > > drivers/pwm/pwm-mediatek.c | 53 ++++++++++++++++++++++++++++++++++++-------- > > 1 file changed, 44 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c > > index 1d78ab1..cdd4d31 100644 > > --- a/drivers/pwm/pwm-mediatek.c > > +++ b/drivers/pwm/pwm-mediatek.c > > @@ -16,6 +16,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -40,11 +41,19 @@ enum { > > MTK_CLK_PWM3, > > MTK_CLK_PWM4, > > MTK_CLK_PWM5, > > + MTK_CLK_PWM6, > > + MTK_CLK_PWM7, > > + MTK_CLK_PWM8, > > MTK_CLK_MAX, > > }; > > > > -static const char * const mtk_pwm_clk_name[] = { > > - "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5" > > +static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { > > + "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", > > + "pwm8" > > +}; > > + > > +struct mtk_pwm_platform_data { > > + unsigned int num_pwms; > > }; > > > > /** > > @@ -59,6 +68,10 @@ struct mtk_pwm_chip { > > struct clk *clks[MTK_CLK_MAX]; > > }; > > > > +static const unsigned int mtk_pwm_reg_offset[] = { > > + 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 > > +}; > > + > > static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) > > { > > return container_of(chip, struct mtk_pwm_chip, chip); > > @@ -103,14 +116,14 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) > > static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, > > unsigned int offset) > > { > > - return readl(chip->regs + 0x10 + (num * 0x40) + offset); > > + return readl(chip->regs + mtk_pwm_reg_offset[num] + offset); > > } > > > > static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, > > unsigned int num, unsigned int offset, > > u32 value) > > { > > - writel(value, chip->regs + 0x10 + (num * 0x40) + offset); > > + writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset); > > } > > > > static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > > @@ -185,6 +198,7 @@ static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) > > > > static int mtk_pwm_probe(struct platform_device *pdev) > > { > > + const struct mtk_pwm_platform_data *data; > > struct mtk_pwm_chip *pc; > > struct resource *res; > > unsigned int i; > > @@ -194,15 +208,22 @@ static int mtk_pwm_probe(struct platform_device *pdev) > > if (!pc) > > return -ENOMEM; > > > > + data = of_device_get_match_data(&pdev->dev); > > + if (data == NULL) > > + return -EINVAL; > > + > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > pc->regs = devm_ioremap_resource(&pdev->dev, res); > > if (IS_ERR(pc->regs)) > > return PTR_ERR(pc->regs); > > > > - for (i = 0; i < MTK_CLK_MAX; i++) { > > + for (i = 0; i < data->num_pwms + 2; i++) { > > pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); > > - if (IS_ERR(pc->clks[i])) > > + if (IS_ERR(pc->clks[i])) { > > + dev_err(&pdev->dev, "clock: %s fail: %ld\n", > > + mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i])); > > return PTR_ERR(pc->clks[i]); > > + } > > } > > > > platform_set_drvdata(pdev, pc); > > @@ -210,7 +231,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) > > pc->chip.dev = &pdev->dev; > > pc->chip.ops = &mtk_pwm_ops; > > pc->chip.base = -1; > > - pc->chip.npwm = 5; > > + pc->chip.npwm = data->num_pwms; > > > > ret = pwmchip_add(&pc->chip); > > if (ret < 0) { > > @@ -228,9 +249,23 @@ static int mtk_pwm_remove(struct platform_device *pdev) > > return pwmchip_remove(&pc->chip); > > } > > > > +static const struct mtk_pwm_platform_data mt2712_pwm_data = { > > + .num_pwms = 8, > > +}; > > + > > +static const struct mtk_pwm_platform_data mt7622_pwm_data = { > > + .num_pwms = 6, > > +}; > > + > > +static const struct mtk_pwm_platform_data mt7623_pwm_data = { > > + .num_pwms = 5, > > +}; > > + > > static const struct of_device_id mtk_pwm_of_match[] = { > > - { .compatible = "mediatek,mt7623-pwm" }, > > - { } > > + { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, > > + { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, > > + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, > > + { }, > > }; > > MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); > > > > From 1583954583842413818@xxx Mon Nov 13 12:40:04 +0000 2017 X-GM-THRID: 1582223927417446326 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread