Received: by 10.223.164.202 with SMTP id h10csp169569wrb; Mon, 13 Nov 2017 04:40:05 -0800 (PST) X-Google-Smtp-Source: AGs4zMbahUM/MM55vMQxD2o4I7gL/L6tZiVwbg0uSSBy9AVyF1LSZg6gNi/KFhaWfoYOdZK2XnAf X-Received: by 10.159.229.203 with SMTP id t11mr8869191plq.190.1510576805178; Mon, 13 Nov 2017 04:40:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510576805; cv=none; d=google.com; s=arc-20160816; b=W+eQ/rOzKdhlQNz4YnOv4AfKLnOh+S4PjccNJFHePQtLm7TrUEYkXq4nMj3YQ3MV0Z kAQwrYgboMfSsVIryjQzXrnUInscjTuhnsXjyrbpAJyhjB2oplRBIGOJHPgw1rUe7ZvI QSh6Dox58k0NUB9Dq4GfZYo/tNMJlBqsqZv6KRLZDxIqhgCDXI8c2/rL0CudhvBcxL8W G8exOhT8GVfRQf9Z+CwZifcEpUUqjHVPHeYex0roTRN40rC0c4HRjlqh8gI1EumrYONi eLBV1lJDlrplcuF6Hk8i3mxXEOJULK99ruP5NsN2iyC4iDZq8imDCQKbHolhtS5TFhpv Vh8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id :arc-authentication-results; bh=Avolrut3O5l68ZT1XD+fxcrxqxrETDoHW1BDwJdvBXA=; b=EqdkvNdjf1xsiqxAXV51Kp2EUGFBjQByFB+QrtIYmm0a391RMyyYOPNL6kQgiKi3HP 9wth8PXFcbZkz7kdvFpgrCNQcOuPvrhnemhCVKfkddpJTjV3endxBbjzqC4T90EQ9tVE c4mePM/UnaXm3X+88mhHuwl69Rn97NDgsX+gBYQe+5JxlL0Xafm3PU/FkWaW+2wT9Us0 B7jqcRZJ+6moMum/HI0GqnK64pV3TNcKZSneekR1hINiMBoEdYHvfSRGTi2/cAKllgpY dTjjmDsGWR5z/OlOAw/rCwkorhK73CYZPX7IIaNBgz51zXEsrenRczydOHoJr2xGma47 6KYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d12si11448808pgn.478.2017.11.13.04.39.51; Mon, 13 Nov 2017 04:40:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752733AbdKMMjO (ORCPT + 95 others); Mon, 13 Nov 2017 07:39:14 -0500 Received: from mailgw01.mediatek.com ([218.249.47.110]:55381 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752526AbdKMMjN (ORCPT ); Mon, 13 Nov 2017 07:39:13 -0500 X-UUID: 15af9c8c97274159a8038c9872f3ec1f-20171113 Received: from mtkcas34.mediatek.inc [(172.27.4.250)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1757489591; Mon, 13 Nov 2017 20:39:07 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 13 Nov 2017 20:39:05 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 13 Nov 2017 20:39:05 +0800 Message-ID: <1510576744.12324.23.camel@mhfsdcap03> Subject: Re: [PATCH v7 1/1] pwm: mediatek: add MT2712/MT7622 support From: Zhi Mao To: , Thierry Reding CC: Thierry Reding , , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , , , , , , Date: Mon, 13 Nov 2017 20:39:04 +0800 In-Reply-To: <1508926261-25015-1-git-send-email-zhi.mao@mediatek.com> References: <1508926261-25015-1-git-send-email-zhi.mao@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thierry, Just have a ping for this patch. Regards Zhi On Wed, 2017-10-25 at 18:11 +0800, Zhi Mao wrote: > Add support to MT2712 and MT7622. > Due to register offset address of pwm7 for MT2712 is not fixed 0x40, > add mtk_pwm_reg_offset array for pwm register offset. > > Reviewed-by: Claudiu Beznea > Reviewed-by: Matthias Brugger > Signed-off-by: Zhi Mao > --- > changee in v7: > - adjust the commit message > > Changes in v6: > - remove "struct mtk_pwm_platform_data" member from "mtk_pwm_chip". > > Changes in v5: > - Add NULL pointer checking for "data" > > drivers/pwm/pwm-mediatek.c | 53 ++++++++++++++++++++++++++++++++++++-------- > 1 file changed, 44 insertions(+), 9 deletions(-) > > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c > index 1d78ab1..cdd4d31 100644 > --- a/drivers/pwm/pwm-mediatek.c > +++ b/drivers/pwm/pwm-mediatek.c > @@ -16,6 +16,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -40,11 +41,19 @@ enum { > MTK_CLK_PWM3, > MTK_CLK_PWM4, > MTK_CLK_PWM5, > + MTK_CLK_PWM6, > + MTK_CLK_PWM7, > + MTK_CLK_PWM8, > MTK_CLK_MAX, > }; > > -static const char * const mtk_pwm_clk_name[] = { > - "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5" > +static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { > + "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", > + "pwm8" > +}; > + > +struct mtk_pwm_platform_data { > + unsigned int num_pwms; > }; > > /** > @@ -59,6 +68,10 @@ struct mtk_pwm_chip { > struct clk *clks[MTK_CLK_MAX]; > }; > > +static const unsigned int mtk_pwm_reg_offset[] = { > + 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 > +}; > + > static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) > { > return container_of(chip, struct mtk_pwm_chip, chip); > @@ -103,14 +116,14 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) > static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, > unsigned int offset) > { > - return readl(chip->regs + 0x10 + (num * 0x40) + offset); > + return readl(chip->regs + mtk_pwm_reg_offset[num] + offset); > } > > static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, > unsigned int num, unsigned int offset, > u32 value) > { > - writel(value, chip->regs + 0x10 + (num * 0x40) + offset); > + writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset); > } > > static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > @@ -185,6 +198,7 @@ static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) > > static int mtk_pwm_probe(struct platform_device *pdev) > { > + const struct mtk_pwm_platform_data *data; > struct mtk_pwm_chip *pc; > struct resource *res; > unsigned int i; > @@ -194,15 +208,22 @@ static int mtk_pwm_probe(struct platform_device *pdev) > if (!pc) > return -ENOMEM; > > + data = of_device_get_match_data(&pdev->dev); > + if (data == NULL) > + return -EINVAL; > + > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > pc->regs = devm_ioremap_resource(&pdev->dev, res); > if (IS_ERR(pc->regs)) > return PTR_ERR(pc->regs); > > - for (i = 0; i < MTK_CLK_MAX; i++) { > + for (i = 0; i < data->num_pwms + 2; i++) { > pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); > - if (IS_ERR(pc->clks[i])) > + if (IS_ERR(pc->clks[i])) { > + dev_err(&pdev->dev, "clock: %s fail: %ld\n", > + mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i])); > return PTR_ERR(pc->clks[i]); > + } > } > > platform_set_drvdata(pdev, pc); > @@ -210,7 +231,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) > pc->chip.dev = &pdev->dev; > pc->chip.ops = &mtk_pwm_ops; > pc->chip.base = -1; > - pc->chip.npwm = 5; > + pc->chip.npwm = data->num_pwms; > > ret = pwmchip_add(&pc->chip); > if (ret < 0) { > @@ -228,9 +249,23 @@ static int mtk_pwm_remove(struct platform_device *pdev) > return pwmchip_remove(&pc->chip); > } > > +static const struct mtk_pwm_platform_data mt2712_pwm_data = { > + .num_pwms = 8, > +}; > + > +static const struct mtk_pwm_platform_data mt7622_pwm_data = { > + .num_pwms = 6, > +}; > + > +static const struct mtk_pwm_platform_data mt7623_pwm_data = { > + .num_pwms = 5, > +}; > + > static const struct of_device_id mtk_pwm_of_match[] = { > - { .compatible = "mediatek,mt7623-pwm" }, > - { } > + { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, > + { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, > + { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, > + { }, > }; > MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); > From 1582223927417446326@xxx Wed Oct 25 10:12:02 +0000 2017 X-GM-THRID: 1582223927417446326 X-Gmail-Labels: Inbox,Category Forums